CY7C68001-56LFC Cypress Semiconductor Corp, CY7C68001-56LFC Datasheet - Page 43

• Manufacturer Part Number: CY7C68001-56LFC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68001-56LFC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

19. Document History Page
Document #: 38-08013 Rev. *K
Description Title: CY7C68001 EZ-USB SX2™ High Speed USB Interface Device
Document Number: 38-08013
REV.
*C
*A
*B
**
ECN No.
123155
126324
129463
111807
Submission
06/07/02
02/07/03
07/02/03
10/07/03
Date
Origin of
Change
MON
MON
BHA
BHA
Minor clean-up and clarification
New Data Sheet
Removed references to IRQ Register and replaced them with references to
Interrupt Status Byte
Modified pin-out description for XTALIN and XTALOUT
Added CS# timing to
Changed Command Protocol example to IFCONFIG (0x01)
Edited PCB Layout Recommendations
Added AR#10691
Added USB high speed logo
Default state of registers specified in section where the register bits are defined
Reorganized timing diagram presentation: First all timing related to synchronous
interface, followed by timing related to asynchronous interface, followed by timing
diagrams common to both interfaces
Provided further information in section 5.3 regarding boot methods
Provided timing diagram that encapsulates ALL relevant signals for a synchronous
and asynchronous slave read and write interface
Added section on (QFN) Package Design Notes
FIFOADR[2:0] Hold Time (t
as follows: SLRD/PKTEND to FIFOADR[2:0] Hold Time: 20 ns; SLWR to
FIFOADR[2:0] Hold Time:70 ns (recommended)
Added information on the polarity of the programmable flag
Fixed the Command Synchronous Write Timing Diagram
Fixed the Command Asynchronous Write Timing Diagram
Added information on the delay required when endpoint configuration registers are
Added Test ID for the USB Compliance Test
Added information on the fact that the SX2 does not automatically respond to
Set/Clear Feature Endpoint (Stall) request, external master intervention required
Added information on accessing undocumented register which are not indexed (for
resetting data toggle)
Added information on requirement of clock stability before releasing reset
Added information on configuration of PF register for full speed
Updated confirmed timing on FIFOADR[2:0] Hold Time (t
FIFO Interface has been updated
Corrected the default bit settings of EPxxFLAGS register
Added information on how to change SLWR/SLRD/SLOE polarities
Added further information on buffering interrupt on initiation of a command read
request
Change the default state of the FNADDR to 0x00
Added further labels on the sequence diagram for synchronous and asynchronous
read and write in single and burst mode
Added information on the maximum delay allowed between each descriptor byte
write once a command write request to register 0x30 has been initiated by the
external master
changed after SX2 has already enumerated
Figure
FAH)
,
Description of Change
Figure
for Asynchronous FIFO Interface has been updated
, and
Figure 13-13.
FAH
)for Asynchronous
CY7C68001
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