ADSP-2171KST-133 Analog Devices Inc, ADSP-2171KST-133 Datasheet - Page 20
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ADSP-2171KST-133
Manufacturer Part Number
ADSP-2171KST-133
Description
Manufacturer
Analog Devices Inc
Datasheet
1.ADSP-2171KST-133.pdf
(52 pages)
Specifications of ADSP-2171KST-133
Device Core Size
16b
Architecture
Enhanced Harvard
Format
Fixed Point
Clock Freq (max)
33.33MHz
Mips
33
Device Input Clock Speed
33.33MHz
Ram Size
10KB
Program Memory Size
24KB
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
128
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
Parameter
Interrupts and Flags
Timing Requirement:
t
t
Switching Characteristic:
t
t
NOTES
1
2
3
4
If IRQx and FI inputs meet t
Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
IRQx = IRQ0, IRQ1, and IRQ2.
Flag Output = FL0, FL1, FL2, and FO.
IFS
IFH
FOH
FOD
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)
IRQx or FI Setup before CLKOUT Low
IRQx or FI Hold after CLKOUT High
Flag Output Hold after CLKOUT Low
Flag Output Delay from CLKOUT Low
IFS
and t
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
OUTPUTS
CLKOUT
FLAG
IRQx
FI
Figure 9. Interrupts and Flags
1, 2, 3
4
4
1, 2, 3
t
t
FOH
FOD
–20–
t
IFH
Min
0.25t
0.25t
0.5t
CK
CK
CK
t
IFS
– 7
+ 15
Max
0.5t
CK
+ 5
REV. A
Unit
ns
ns
ns
ns