CY39200V388-83MGC Cypress Semiconductor Corp, CY39200V388-83MGC Datasheet - Page 22

• Manufacturer Part Number: CY39200V388-83MGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY39200V388-83MGC

• Family Name: Delta39K
• Memory Type: SRAM
• # Macrocells: 3072
• Number Of Usable Gates: 200000
• Propagation Delay Time: 15ns
• # I/os (max): 294
• Operating Supply Voltage (typ): 2.5/3.3V
• Ram Bits: 491520
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

Switching Characteristics—Parameter Values
Input and Output Standard Timing Delay
Adjustments
All the timing specifications in this data sheet are specified
based on LVCMOS compliant inputs and outputs (fast slew
rates).
are configured to operate at other standards.
Document #: 38-03039 Rev. *I
t
f
f
f
P
f
JTAG Parameters
t
t
t
t
t
t
t
t
Notes:
14. Refer to page 11 and the application note titled “Delta39K PLL and Clock Tree” for details on the PLL operation.
15. For “slow slew rate” output delay adjustments, refer to Warp software’s static timing analyzer results.
16. These delays are based on falling edge output. The rising edge delay depends on the size of pull-up resistor and termination voltage.
INDUTY
PLLO
PLLI
PLLVCO
MPLLI
JCKH
JCKL
JCP
JSU
JH
JCO
JXZ
JZX
SAPLLI
Parameter
LVTTL – 12 mA
LVTTL – 16 mA
LVTTL – 24 mA
[14]
LVTTL – 2 mA
LVTTL – 4 mA
LVTTL – 6 mA
LVTTL – 8 mA
I/O Standard
[14]
LVCMOS18
[15]
LVCMOS3
LVCMOS2
LVCMOS
3.3V PCI
SSTL3 II
SSTL3 I
GTL+
Apply following adjustments if the inputs and outputs
Min.
12.5
–0.3
100
6.2
40
25
25
50
10
10
0.02
t
–0.14
–0.15
IOD
233
2.75
0.16
0.14
0.41
–0.4
1.8
1.8
1.2
0.6
1.6
0
0
[16]
Max.
Fast Slew Rate
+0.3
266
133
266
60
50
20
20
20
t
0.6
EA
0.05
0.1
0.7
0.3
0.2
0
0
0
0
0
0
0
0
0
[16]
Min.
12.5
–0.3
100
6.2
40
25
25
50
10
10
Output Delay Adjustments
t
0.9
200
ER
0.1
0.1
0
0
0
0
0
0
0
0
0
0
0
0
[16]
Max.
+0.3
266
133
266
60
50
20
20
20
(additional delay to fast slew rate)
t
IODSLOW
2.6
2.5
2.5
2.4
2.3
2.0
1.6
2.0
2.0
2.0
2.1
2.0
2.0
2.0
2.0
Over the Operating Range (continued)
Min.
12.5
–0.3
100
6.2
40
25
25
50
10
10
Slow Slew Rate
181
Max.
t
+0.3
266
133
266
EASLOW
60
50
20
20
20
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
Min.
12.5
–0.3
100
6.2
40
25
25
50
10
10
t
ERSLOW
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
125
Max.
+0.3
200
100
266
60
50
20
20
20
t
Delta39K™ ISR™
IOIN
Input Delay Adjustments
0.1
0.2
0.5
0.5
0.5
0.5
0
0
0
0
0
0
0
0
0
Min.
12.5
–0.3
100
6.2
40
25
25
50
10
10
CPLD Family
t
83
CKIN
0.1
0.2
0.4
0.4
0.3
0.3
0
0
0
0
0
0
0
0
0
Max.
+0.3
200
100
266
60
50
20
20
20
Page 22 of 86
t
IOREGPIN
MHz
MHz
MHz
Unit
KHz
0.2
0.4
0.3
0.2
0.3
0.3
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
0
0
0
0
0
%
%
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