CY7B994V-2AI Cypress Semiconductor Corp, CY7B994V-2AI Datasheet - Page 10

• Manufacturer Part Number: CY7B994V-2AI
• Manufacturer: Cypress Semiconductor Corp
• Type: Zero Delay PLL Clock Bufferr

Specifications of CY7B994V-2AI

• Number Of Elements: 1
• Supply Current: 250mA
• Pll Input Freq (min): 24MHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Output Frequency Range: 24 to 200MHz
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-07127 Rev. *F
Switching Characteristics
AC Test Loads and Waveform
Notes:
18. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
19. Tested initially and after any design or process changes that may affect these parameters.
20. Rise and fall times are measured between 2.0V and 0.8V.
21. f
22. t
23. UI = Unit Interval. Examples: 1 UI is a full period. 0.1UI is 10% of period.
24. Measured at 0.5V deviation from starting voltage.
25. For t
26. These figures are for illustrations only. The actual ATE loads may vary.
TTB
t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
PDDELTA
REFpwh
REFpwl
r
LOCK
RELOCK1
RELOCK2
ODCV
PWH
PWL
PDEV
OAZ
OAZ
/t
f
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle
jitter, and dynamic phase error. TTB will be equal to or smaller than the maximum specified value at a given frequency.
NOM
PWH
OZA
must be within the frequency range defined by the same FS state.
is measured at 2.0V. t
minimum, C
Total Timing Budget window (same frequency and phase)
18]
Propagation Delay difference between two devices
REF input (Pulse Width HIGH)
REF input (Pulse Width LOW)
Output Rise/Fall Time
PLL Lock Time From Power-up
PLL Relock Time (from same frequency, different phase)
with Stable Power Supply
PLL Relock Time (from different frequency, different phase)
with Stable Power Supply
Output duty cycle deviation from 50%
Output HIGH time deviation from 50%
Output LOW time deviation from 50%
Period deviation when changing from reference to
reference
DIS[1:4]/FBDIS HIGH to output high-impedance from
ACTIVE
DIS[1:4]/FBDIS LOW to output ACTIVE from output
high-impedance
For LOCK output only
R1 = 910Ω
R2 = 910Ω
C
L
< 30 pF
L
= 0 pF. For t
(Includes fixture and
probe capacitance)
[14, 24]
[23]
PWL
is measured at 0.8V.
[24, 25]
OZA
maximum, C
Over the Operating Range
[20]
For all other outputs
R1 = 100Ω
R2 = 100Ω
C
Description
L
[26]
[21]
< 25 pF to 185 MHz
GND
3.3V
L
[19]
or 10 pF at 200 MHz
< 1 ns
[19]
= 25 pF to 185 MHz or 10 pF to 200 MHz.
(a) LVTTL AC Test Load
(b) TTL Input Test Waveform
[13]
[22]
[22]
0.8V
2.0V
[9, 10, 11, 12, 13]
OUTPUT
[17]
[17,
C
L
Min.
0.15
–1.0
2.0
2.0
1.0
0.5
(continued)
–
–
–
–
–
–
–
–
CY7B993/4V-2
3.3V
Typ.
2.0V
–
–
–
–
–
–
R1
R2
0.8V
< 1 ns
0.025
Max.
1000
500
200
500
2.0
1.0
1.5
2.0
10
10
14
–
–
Min.
0.15
–1.0
2.0
2.0
1.0
0.5
–
–
–
–
–
–
–
–
CY7B993/4V-5
Typ.
RoboClock
–
–
–
–
–
–
CY7B993V
CY7B994V
0.025
Max.
1000
700
200
500
2.0
1.0
1.5
2.0
10
10
14
Page 10 of 15
–
–
Unit
ms
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ps
ps
UI

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