CY7C009V-15AC Cypress Semiconductor Corp, CY7C009V-15AC Datasheet
CY7C009V-15AC
Specifications of CY7C009V-15AC
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CY7C009V-15AC Summary of contents
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... CY7C008V CY7C018V CY7C009V CY7C019V 3.3V 64K/128K x 8/9 Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 64K x 8 organization (CY7C008) • 128K x 8 organization (CY7C009) • 64K x 9 organization (CY7C018) • 128K x 9 organization (CY7C019) • ...
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... Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin. The CY7C008V/009V and CY7018V/019V are available in and dual-port 100-pin Thin Quad Plastic Flatpacks (TQFP). 100-Pin TQFP (Top View CY7C009V (128K x 8) CY7C008V (64K CY7C008V/009V CY7C018V/019V ...
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Pin Configurations (continued) 100 A7L 3 A8L 4 A9L 5 A10L 6 A11L 7 A12L 8 A13L 9 A14L 10 A15L 11 [5] A16L 12 VCC ...
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... Supply Voltage to Ground Potential ............... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State............................–0. Notes: 6. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 7. Industrial parts are available in CY7C009V and CY7C019V only. Document #: 38-06044 Rev. *C Description Chip Enable (CE is LOW when CE Read/Write Enable ...
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Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage ( Output LOW Voltage ( Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current IX I Output Leakage ...
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Switching Characteristics Over the Operating Range Parameter Description READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Output Hold From Address Change OHA [11 LOW to Data Valid ACE t OE LOW to ...
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Switching Characteristics Over the Operating Range Parameter Description t R/W HIGH after BUSY HIGH (Slave) WH [17] t BUSY HIGH to Data Valid BDD [16] INTERRUPT TIMING t INT Set Time INS t INT Reset Time INR SEMAPHORE TIMING t ...
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Switching Waveforms Read Cycle No.1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Read Cycle No.2 (Either Port CE/OE Access DATA OUT CURRENT I SB [19, 21, 22, 23] ...
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Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [28 R/W NOTE 30 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [28 R/W DATA IN Notes: 24. ...
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Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A –A ...
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Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 36 LOW. ...
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Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Busy Timing Diagram No. 2 (Address ...
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... Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE FFFF (1FFFF for CY7C009V/19V R/W L INT R [39] t INS Right Side Clears INT : R ADDRESS R INT R Right Side Sets INT : L ADDRESS WRITE FFFE (1FFFF for CY7C009V/19V R/W R INT L [39] t INS Right Side Clears INT ...
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Architecture The CY7C008V/009V and CY7018V/019V consist of an array of 64K and 128K words of 8 and 9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access ...
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... Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore Notes: 40. A and A , 1FFFF/1FFFE for the CY7C009V/19V. 0L–16L 0R–16R 41. If BUSY = L, then no change. R 42. If BUSY = L, then no change. ...
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... CY7C008V-20AC 25 CY7C008V-25AC CY7C008V-25AXC 64K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C018V-15AC 20 CY7C018V-20AC 25 CY7C018V-25AC 128K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C009V-15AC CY7C009V-15AXC 20 CY7C009V-20AC CY7C009V-20AI CY7C009V-20AXI 25 CY7C009V-25AC CY7C009V-25AXC 128K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C019V-15AC CY7C019V-15AXC 20 CY7C019V-20AC CY7C019V-20AXC ...
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... Document #: 38-06044 Rev. *C © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...
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... Document #: 38-06044 Rev. *C Description of Change Change from Spec number: 38-00669 to 38-06044 Change pin 85 from BUSYL to BUSYR (pg. 3) Power up requirements added to Maximum Ratings Information Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C008V-25AXC, CY7C009V-15AXC, CY7C009V-20AXI, CY7C009V-25AXC, CY7C019V-15AXC, CY7C019V-20AXC, CY7C019V-20AXI, CY7C019V-25AXC CY7C008V/009V CY7C018V/019V Page [+] Feedback ...