CY7C028V-15AC Cypress Semiconductor Corp, CY7C028V-15AC Datasheet
CY7C028V-15AC
Specifications of CY7C028V-15AC
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CY7C028V-15AC Summary of contents
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... True Dual-Ported memory cells which allow simultaneous access of the same memory location ■ 32K x 16 organization (CY7C027V/027VN/027AV ■ 64K x 16 organization (CY7C028V) ■ 32K x 18 organization (CY7C037V/037AV ■ 64K x 18 organization (CY7C038V) ■ 0.35 micron CMOS for optimum speed and power ■ ...
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... VCC 15 R/WL 16 OEL 17 GND 18 GND 19 I/O15L 20 I/O14L 21 I/O13L 22 I/O12L 23 I/O11L 24 I/O10L Note 1. This pin is NC for CY7C027V/027VN/027AV. Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V Figure 1. 100-Pin TQFP (Top View CY7C028V (64K x 16 CY7C037V/037AV/038V A9R 74 A10R 73 A11R 72 A12R 71 A13R 70 A14R 69 A15R [ LBR 65 UBR 64 CE0R 63 CE1R ...
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Pin Configurations (continued) 100 A9L 1 A10L 2 A11L 3 A12L 4 A13L 5 A14L 6 [2] A15L 7 LBL 8 UBL 9 CE0L 10 CE1L 11 SEML 12 R/WL 13 OEL 14 VCC 15 GND 16 ...
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... CY7C027V/027VN/027AV/37V, FFFF for the CY7C028V/38V) is the mailbox for the right port and the second-highest memory location (7FFE for the CY7C027V/027VN/027AV/037V/037AV, FFFE for the CY7C028V/38V) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is ≥ V ...
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The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy ...
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... Input Capacitance IN C Output Capacitance OUT Notes 2. Pulse width < 20 ns. 3. Industrial parts are available in CY7C028V and CY7C038V only 1/t = All inputs cycling 1/t (except output enable means no address or control lines change. This applies only to inputs at CMOS level standby I MAX ...
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R1 = 590Ω OUTPUT 435Ω (a) Normal Load (Load 1) 3.0V GND Switching Characteristics Over the Operating Range Parameter Description Read Cycle t Read Cycle Time RC t Address to Data Valid AA ...
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Switching Characteristics Over the Operating Range Parameter Description t Data Hold From Write End HD [9, 10] t R/W LOW to High Z HZWE [9 ,10] t R/W HIGH to Low Z LZWE [36] t Write Pulse to Data Delay ...
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Switching Waveforms Figure 4. Read Cycle No. 1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) CE and DATA OUT ...
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Switching Waveforms (continued) Figure 7. Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [24,25 R/W NOTE 27 DATA OUT DATA IN Figure 8. Write Cycle No Controlled Timing ADDRESS [24,25 R/W ...
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Switching Waveforms (continued) Figure 9. Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Figure 10. Timing Diagram of Semaphore Contention A – R/W L ...
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Switching Waveforms (continued) Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Figure 12. Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 33. CE ...
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Switching Waveforms (continued) Figure 13. Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Figure 14. Busy Timing ...
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... Switching Waveforms (continued) Left Side Sets INT : R ADDRESS WRITE 7FFF (FFFF for CY7C028V/38V R/W L INT R [36] t INS Right Side Clears INT : R ADDRESS R INT R : Right Side Sets INT L ADDRESS WRITE 7FFE (FFFE for CY7C028V/38V R/W R INT L [36] t INS Left Side Clears INT ...
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... Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore Notes 37. A and A ,FFFF/FFFE for the CY7C028V/038V. 0L–15L 0R–15R 38. If BUSY =L, then no change. R 39. If BUSY =L, then no change. ...
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... Speed (ns) Ordering Code 15 CY7C027V-15AC CY7C027V-15AXC CY7C027VN-15AXC 20 CY7C027V-20AC CY7C027V-20AXC 25 CY7C027V-25AC CY7C027V-25AXC CY7C027AV-25AXI 64K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C028V-15AC CY7C028V-15AXC 20 CY7C028V-20AC CY7C028V-20AXC CY7C028V-20AI CY7C028V-20AXI 25 CY7C028V-25AC CY7C028V-25AXC 32K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C037V-15AC CY7C037V-15AXC 20 CY7C037V-20AC CY7C037AV-20AXC ...
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Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V 51-85048-*C Page [+] Feedback ...
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... Document History Page Document Title: CY7C027V/027VN/027AV/CY7C028V/037V/037AV/038V 3.3V 32K/64K x 16/18 Dual Port Static RAM Document Number: 38-06078 Orig. of Rev. ECN No. Change ** 237626 YDT *A 259110 JHX *B 2623540 VKN/PYRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...