CY7C09199-6AC Cypress Semiconductor Corp, CY7C09199-6AC Datasheet - Page 5
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CY7C09199-6AC
Manufacturer Part Number
CY7C09199-6AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C09199-6AC.pdf
(19 pages)
Specifications of CY7C09199-6AC
Density
1.125Mb
Access Time (max)
15ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
52MHz
Operating Supply Voltage (typ)
5V
Address Bus
17b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
450mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
9b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant
Pin Definitions
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied .. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.3V to +7.0V
DC Voltage Applied to
Outputs in High Z State ................................. –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
Document #: 38-06039 Rev. *A
A
ADS
CE
CLK
CNTEN
CNTRST
I/O
OE
R/W
FT/PIPE
GND
NC
V
Note:
8.
9.
0L
CC
Left Port
0L
0L
L
–A
The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
Industrial parts are available in CY7C09099 and CY7C09199 only.
L
L
L
,CE
–I/O
16L
L
L
1L
L
8L
A
ADS
CE
CLK
CNTEN
CNTRST
I/O
OE
R/W
FT/PIPE
Right Port
0R
0R
0R
R
–A
R
R
R
–I/O
,CE
16R
R
R
[8]
1R
R
8R
Address Inputs (A
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads the
burst counter with the address present on the address pins.
Chip Enable Input. To select either the left or right port, both CE
their active states (CE
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output (I/O
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
0
A
15
0
for 64K; and A
V
0
IL
–I/O
and CE
7
for x8 devices; I/O
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
Latch-Up Current...................................................... >200mA
Operating Range
Commercial
Industrial
1
0
V
Range
A
Description
IH
16
).
[9]
for 128K devices).
0
–I/O
8
Temperature
0°C to +70°C
40°C to +85°C
for x9 devices).
Ambient
0
AND CE
CY7C09089/99
CY7C09189/99
1
must be asserted to
5V
5V
Page 5 of 19
V
MAX
CC
10%
10%
.
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