CY7C09289-6AC Cypress Semiconductor Corp, CY7C09289-6AC Datasheet - Page 2

• Manufacturer Part Number: CY7C09289-6AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09289-6AC

• Density: 1Mb
• Access Time (max): 15ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 53MHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 16b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 450mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 16b
• Number Of Words: 64K
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
The CY7C09279/89 and CY7C09379/89 are high-speed syn-
chronous CMOS 32K, and 64K x 16/18 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory.
isters on control, address, and data lines allow for minimal set-
up and hold times. In pipelined output mode, data is registered
for decreased cycle time. Clock to data valid t
(pipelined). Flow-through mode can also be used to bypass
the pipelined output register to eliminate access latency. In
flow-through mode data will be available t
address is clocked into the device. Pipelined output or flow-
through mode is selected via the FT/PIPE pin.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW-
to-HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
Pin Configurations
Notes:
Document #: 38-06040 Rev. *A
5.
6.
7.
When writing simultaneously to the same location, the final value cannot be guaranteed.
This pin is NC for CY7C09279.
For CY7C09279, pin #18 connected to V
through device.
[7]
CNTRSTL
FT/PIPEL
A15L
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
CE0L
CE1L
R/WL
A10L
A11L
A12L
A13L
A14L
GND
VCC
OEL
UBL
A9L
LBL
NC
NC
[6]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100
26
99
27
98
28
CC
97
29
is equivalent to an IDT x16 pipelined device; connecting pin #18 and #58 to GND is equivalent to an IDT x16 flow-
96
30
CD1
95
31
CY7C09289 (64K x 16)
CY7C09279 (32K x 16)
= 15 ns after the
94
32
CD2
93
33
100-Pin TQFP (Top View)
= 6.5 ns
92 91 90
34 35 36
[5]
Reg-
[1]
89
37
88
38
87 86
39 40
A HIGH on CE
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
85
41
84
42
83 82 81
43 44 45
0
or LOW on CE
80
46
79
47
78 77
48 49
1
76
50
for one clock cycle will power
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C09279/89
CY7C09379/89
A9R
A10R
A11R
A12R
A13R
A14R
A15R
NC
NC
LBR
UBR
CE0R
CE1R
CNTRSTR
GND
R/WR
OER
FT/PIPER
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
0
LOW and CE
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