CY7C09579V-83AI Cypress Semiconductor Corp, CY7C09579V-83AI Datasheet - Page 21
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CY7C09579V-83AI
Manufacturer Part Number
CY7C09579V-83AI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C09579V-83AI.pdf
(32 pages)
Specifications of CY7C09579V-83AI
Density
1.125Mb
Access Time (max)
6ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
45MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
15b
Package Type
TQFP
Operating Temp Range
-40C to 85C
Number Of Ports
2
Supply Current
385mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Word Size
36b
Number Of Words
32K
Lead Free Status / Rohs Status
Not Compliant
Switching Waveforms
Counter Reset (Pipelined Outputs)
Notes
Document Number: 38-06054 Rev. *D
59. Test conditions used are Load 2.
60. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
61. CE = B0 = B1 = B2 = B3 = V
62. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
63. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATA
INTERNAL
ADDRESS
ADDRESS
DATA
CNTRST
during a valid WRITE cycle.
DATA
CNTEN
ADS
R/W
CLK
OUT
[63
IN
t
SRST
A
x
t
HRST
t
COUNTER
CH2
RESET
t
CYC2
IL
.
t
CL2
t
SW
t
SD
(continued)
D
0
t
t
HW
HD
ADDRESS 0
WRITE
[59, 60, 61, 62, 63]
0
t
CKLZ
ADDRESS 0
READ
ADDRESS 1
t
CD2
READ
1
Q
A
0
n
ADDRESS A
t
READ
CD2
OUT
should be in the High-Impedance state
A
t
SA
n
n
A
Q
m
1
t
ADDRESS A
HA
READ
CY7C09569V
CY7C09579V
A
m
m
Q
A
n
p
Page 21 of 32
A
p
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