CY7C1367A-150AC Cypress Semiconductor Corp, CY7C1367A-150AC Datasheet - Page 5

• Manufacturer Part Number: CY7C1367A-150AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1367A-150AC

• Density: 9Mb
• Access Time (max): 3.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 380mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Lead Free Status / Rohs Status: Not Compliant

256K X 36 Pin Descriptions
2A, 3A, 5A, 6A, 3B,
5B, 6B, 2C, 3C, 5C,
6C, 2R, 6R, 3T, 4T,
X36 PBGA Pins
(not available for
PBGA)
4M
4N
5G
3G
4H
4G
3R
4P
5T
5L
3L
4K
4E
2B
4F
4A
4B
7T
100, 99, 82, 81,
43 (TA Version)
X36 QFP Pins
35, 34, 33, 32,
44, 45, 46, 47,
92 (T Version)
Version only)
48, 49, 50
92 (for TA
37
36
93
94
95
96
87
88
89
98
97
86
83
84
85
31
64
MODE
ADSP
ADSC
Name
BWb
BWd
BWE
BWa
BWc
CLK
ADV
CE
CE
GW
CE
OE
A0
A1
ZZ
A
2
2
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Static
Input-
Type
Input
5
Addresses: These inputs are registered and must meet the set
up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
Byte Write: A byte write is LOW for a WRITE cycle and HIGH
for a READ cycle. BWa controls DQa. BWb controls DQb. BWc
controls DQc. BWd controls DQd. Data I/O are high imped-
ance if either of these inputs are LOW, conditioned by BWE
being LOW.
Write Enable: This active LOW input gates byte write opera-
tions and must meet the set-up and hold times around the
rising edge of CLK.
Global Write: This active LOW input allows a full 36-bit Write
to occur independent of the BWE and BWn lines and must
meet the set-up and hold times around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables,
write control, and burst control inputs on its rising edge. All
synchronous inputs must meet set up and hold times around
the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the de-
vice and to gate ADSP .
Chip Enable: This active HIGH input is used to enable the de-
vice.
Chip Enable: This active LOW input is used to enable the de-
vice. Not available for B and T package versions.
Output Enable: This active LOW asynchronous input enables
the data output drivers.
Address Advance: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
Address Status Processor: This active LOW input, along with
CE being LOW, causes a new external address to be regis-
tered and a READ cycle is initiated using the new address.
Address Status Controller: This active LOW input causes de-
vice to be deselected or selected along with new external ad-
dress to be registered. A Read or Write cycle is initiated de-
pending upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects
Interleaved Burst.
Snooze: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Description