CY7C138-35JC Cypress Semiconductor Corp, CY7C138-35JC Datasheet
CY7C138-35JC
Specifications of CY7C138-35JC
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CY7C138-35JC Summary of contents
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... Semaphores included to permit software handshaking between ports • INT flag for port-to-port communication • Available in 68-pin PLCC • Pb-Free packages available Functional Description The CY7C138 and CY7C139 are high-speed CMOS and dual-port static RAMs. Various arbitration schemes Logic Block Diagram R ...
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... FFE and is cleared L when left port reads location FFE. INT FFF and is cleared when right port reads location FFF. Busy Flag Master or Slave Select Power Ground 7C138-15 7C138-25 7C139-15 7C139- 220 180 60 40 CY7C138 CY7C139 INT L BUSY L ...
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... < 0.2V One Port Com’ > V – 0.2V Ind V > V – 0. < 0.2V, Active IN [7] Port Outputs MAX CY7C138 CY7C139 Ambient Temperature V CC ° ° + ± 10% ° ° – + ± 10% 7C138-15 7C138-25 7C139-15 7C139-25 Min. Max. Min. Max. Unit 2.4 2 ...
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... Test Conditions T = 25° MHz 5. 250Ω TH OUTPUT C = 30pF V = 1.4V TH (b) Thé venin Equivalent ( Load 1) ALL INPUT PULSES 90% 90% 10% 10% < < CY7C138 CY7C139 7C138-35 7C138-55 7C139-35 7C139-55 Min. Max. Min. Max. Unit 2.4 2.4 V 0.4 0.4 V 2.2 2.2 V 0.8 0.8 V µA – ...
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... Document #: 38-06037 Rev. *B [9] 7C138-15 7C138-25 7C139-15 7C139-25 Min. Max. Min. Max Note 15 Note 15 is less than t and t is less than t HZCE LZCE HZOE – t (actual – t (actual). WDD PWE DDD SD CY7C138 CY7C139 7C138-35 7C138-55 7C139-35 7C139-55 Min. Max. Min. Max. Unit ...
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... L, SEM = H when accessing RAM SEM = L when accessing semaphores. L Document #: 38-06037 Rev. *B [9] (continued) 7C138-15 7C138-25 7C139-15 7C139-25 Min. Max. Min. Max [16, 17 [16, 18, 19] t ACE t DOE LZOE DATA VALID CY7C138 CY7C139 7C138-35 7C138-55 7C139-35 7C139-55 Min. Max. Min. Max. Unit DATA VALID t HZCE t HZOE t PD Page [+] Feedback ...
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... R/W must be HIGH during all address transitions. Document #: 38-06037 Rev. *B [20, 21 MATCH t PWE t SD VALID MATCH t DDD t WDD [22, 23, 24 SCE PWE t SD DATA VALID HIGH IMPEDANCE PWE HZWE SD CY7C138 CY7C139 t HD VALID LZOE ) to allow the I/O drivers to turn off and data to Page [+] Feedback ...
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... CE = HIGH for the duration of the above timing (both write and read cycle). Document #: 38-06037 Rev. *B [22, 24, 25 SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE [26 VALID ADDRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP READ CYCLE CY7C138 CY7C139 LZWE t OHA t ACE DATA VALID OUT t DOE Page [+] Feedback ...
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... SPS Document #: 38-06037 Rev. *B [27, 28, 29] MATCH t SPS MATCH [21 MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE HIGH L CY7C138 CY7C139 BHA t BDD t DDD VALID Page [+] Feedback ...
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... BUSY will be asserted. PS Document #: 38-06037 Rev. *B [30] ADDRESS MATCH BLC ADDRESS MATCH BLC [30 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C138 CY7C139 t BHC t BHC Page [+] Feedback ...
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... R deasserted first 32 depends on which enable pin (CE or R/W INS INR L Document #: 38-06037 Rev WRITE FFF t [31 [32] INR t WC WRITE FFE t [31] HA [32] t INR ) is asserted last. L CY7C138 CY7C139 t RC READ FFF t RC READ FFE Page [+] Feedback ...
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... Architecture The CY7C138/9 consists of an array of 4K words of 8/9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port– ...
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... Right port is granted access to semaphore change. Left port is denied access 0 1 Left port obtains semaphore port accessing semaphore address 1 0 Right port obtains semaphore port accessing semaphore 0 1 Left port obtains semaphore port accessing semaphore CY7C138 CY7C139 Operation Right Port R INT 0- FFE ...
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... AMBIENT TEMPERATURE (°C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 10 4. 25° 200 400 600 800 1000 CAPACITANCE (pF) CY7C138 CY7C139 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 200 160 120 25° 5.0 0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs ...
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... Ordering Information 4K x8 Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C138-15JC CY7C138-15JXC 25 CY7C138-25JC CY7C138-25JXC CY7C138-25JI 35 CY7C138-35JC CY7C138-35JI 55 CY7C138-55JC CY7C138-55JI 4K x9 Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C139-15JC 25 CY7C139-25JC CY7C139-25JXC CY7C139-25JI 35 CY7C139-35JC CY7C139-35JI 55 CY7C139-55JC CY7C139-55JI Package Diagram 68-Lead Pb-Free Plastic Leaded Chip Carrier J81 All products and company names mentioned in this document may be the trademarks of their respective holders. ...
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... Document History Page Document Title: CY7C138/CY7C139 4K x 8/9 Dual-Port Static RAM Document Number: 38-06037 Issue REV. ECN NO. Date ** 110180 09/29/01 *A 122287 12/27/02 *B 393403 See ECN Document #: 38-06037 Rev. *B Orig. of Change Description of Change SZV Change from Spec number: 38-00536 to 38-06037 RBI Power up requirements added to Maximum Ratings Information ...