CY7C342B-35JI Cypress Semiconductor Corp, CY7C342B-35JI Datasheet - Page 7

• Manufacturer Part Number: CY7C342B-35JI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C342B-35JI

• Family Name: MAX®
• Memory Type: EPROM
• # Macrocells: 128
• Number Of Usable Gates: 2500
• Frequency (max): 40MHz
• Propagation Delay Time: 35ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 52
• Operating Supply Voltage (typ): 5V
• In System Programmable: No
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-03014 Rev. *B
Commercial and Industrial External Asynchronous Switching Characteristics
Commercial and Industrial Typical Internal Switching Characteristics
t
t
t
f
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
AWH
AWL
ACNT
ACNT
IN
IO
EXP
LAD
LAC
OD
ZX
XZ
RSU
RH
LATCH
RD
COMB
IC
ICS
FD
PRE
CLR
PIA
IN
IO
EXP
LAD
LAC
OD
ZX
XZ
RSU
RH
LATCH
RD
7. C1 = 5 pF.
8. Sample tested only for an output change of 500 mV.
9. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial
Parameter
[8]
[8]
operation.
[9]
Asynchronous Clock Input HIGH Time
Asynchronous Clock Input LOW Time
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable Delay
Output Buffer Disable Delay
Register Set-Up Time Relative to Clock Signal at Register
Register Hold Time Relative to Clock Signal at Register
Flow Through Latch Delay
Register Delay
Transparent Mode Delay
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Programmable Interconnect Array Delay Time
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable Delay
Output Buffer Disable Delay
Register Set-Up Time Relative to Clock Signal at Register
Register Hold Time Relative to Clock Signal at Register
Flow Through Latch Delay
Register Delay
USE ULTRA37000
Description
Description
[3]
[3]
[7]
[7]
[3]
[3]
ALL NEW DESIGNS
[5]
[5]
[5]
TM
FOR
Min.
Min.
7C342B-15
7C342B-15
2
7
6
4
50
11
9
Over Operating Range
Max.
Over Operating Range (continued)
Max.
10
12
12
10
10
10
20
3
3
8
8
5
3
5
5
1
1
1
6
0
1
3
3
5
6
5
3
1
Min.
Min.
7C342B–20
7C342B-20
10
14
11
40
1
8
6
CY7C342B
Max.
Max.
25
10
12
13
14
14
12
Page 7 of 14
11
11
4
4
5
3
5
5
1
1
1
8
0
1
3
3
7
6
5
4
2
Unit
33.3
Unit
16
14
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
8
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