IMIB9940LBL Cypress Semiconductor Corp, IMIB9940LBL Datasheet - Page 3

• Manufacturer Part Number: IMIB9940LBL
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Driverr

Specifications of IMIB9940LBL

• Number Of Clock Inputs: 2
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVCMOS/LVPECL/LVTTL
• Mounting: Surface Mount
• Pin Count: 32
• Quiescent Current: 5mA
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-07105 Rev. *C
Maximum Ratings
Maximum Input Voltage Relative to V
Maximum Input Voltage Relative to V
Storage Temperature: ................................–65 C to + 150 C
Operating Temperature: ................................ –40 C to +85 C
Maximum ESD protection ............................................... 2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................±20 mA
DC Parameters
AC Parameters
V
V
I
I
V
V
V
V
I
Z
C
F
t
t
FoutDC
T
T
Notes:
10. Across temperature and voltage ranges, includes output skew.
IL
IH
DDQ
PD
PD
2.
3.
4.
5.
6.
7.
8.
9.
skew
skew
Parameter
IL
IH
PP
CMR
OL
OH
out
max
in
Parameter
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power suppl sequencing is NOT required.
Inputs have pull-up/pull-down resistors that effect input current.
The V
range and the input lies within the V
Driving series or parallel terminated 50
Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
Outputs driving 50 transmission lines.
50% input duty cycle.
Outputs loaded with 30 pF each.
(pp)
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the V
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Peak-to-Peak Input Voltage PECL_CLK
Common Mode Range
PECL_CLK
Output Low Voltage
Output High Voltage
Quiescent Supply Current
Output Impedance
Input Capacitance
Maximum Input Frequency
PECL_CLK to Q Delay
TTL_CLK to Q Delay
Output Duty Cycle
Output-to-Output Skew
Part-to-Part Skew
V
V
DD
DD
[2]
= 3.3V ±5% or 2.5V ±5%, V
= 3.3V ±5% or 2.5V ±5%, V
Description
Description
PP
[3]
[10]
[3]
[7, 8, 9]
specification.
[5]
SS
DD
(or 50
[5]
[7, 9]
: ............ V
: ............. V
[4]
[7, 9]
[7, 9]
to V
DD
/2) transmission lines.
DD
SS
V
V
V
V
Measured at V
V
V
PECL, V
PECL, V
DDC
DDC
– 0.3V
+ 0.3V
DD
DD
DD
DD
DD
DD
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V, Fin = 150 MHz
= 2.5V, Fin = 150 MHz
= 3.3V ±5% or 2.5V ±5%, T
= 3.3V ±5% or 2.5V ±5%, T
All other inputs
All other inputs
V
V
I
I
I
V
V
OL
OH
OH
DD
DD
DD
DD
DDC
DDC
= 20 mA
= –20 mA, V
= –20 mA, V
Conditions
= 3.3V
= 2.5V
= 3.3V
= 2.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
range:
V
Unused inputs must always be tied to an appropriate logic
voltage level (either V
= 3.3V
= 2.5V
Conditions
SS
DD
/2
< (V
in
DDC
DDC
or V
= 3.3V
= 2.5V
out
) < V
A
A
= –40°C to +85°C
= –40°C to +85°C
SS
DD
V
V
in
Min.
2.0
2.6
1.8
2.3
DD
DD
45
and V
.
or V
–
–
–
–
–
Min.
V
500
2.0
2.4
1.8
11
–
–
–
–
9
–
SS
– 1.4
– 1.0
DD
out
).
Typ.
should be constrained to the
3.5
4.0
3.3
3.8
–
–
–
–
–
–
Typ.
14
18
–
–
–
–
–
–
–
–
–
–
2
4
[6]
V
V
Max.
200
150
200
4.0
5.2
3.8
4.4
1.4
2.2
DD
DD
55
Max.
–200
1000
V
200
0.8
0.5
19
26
–
–
5
–
DD
– 0.6
– 0.6
B9940L
Page 3 of 5
Units
MHz
ns
ns
ps
ns
%
Unit
mV
mA
µA
µA
pF
V
V
V
V
V
V
V
CMR
[+] Feedback