IMIC9530CT Cypress Semiconductor Corp, IMIC9530CT Datasheet - Page 2

• Manufacturer Part Number: IMIC9530CT
• Manufacturer: Cypress Semiconductor Corp

Specifications of IMIC9530CT

• Function: Clock Generator
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Package Type: TSSOP
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-07033 Rev. *C
Pin Description
Notes:
3
4
1
24*
25*
18
31
6*, 7*
43*, 42*
20*, 21*, 22*
27*
48
47
11, 14
38, 35
2, 44, 46
23, 29, 30
9, 10, 12, 15,
16
40, 39, 37, 34,
33
5, 8, 13, 17,
19, 26, 28, 32,
36, 41, 45
2. Pin numbers ending with * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is
3. A bypass capacitor (0.1 µF) should be placed as close as possible to each V
4. PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s).
connected to them.
filtering characteristic will be cancelled by the lead inductance of the trace.
Pin
[2]
CLKA (0:4) VDDA
CLKB (0:4) VDDB
AGOOD#
BGOOD#
SA(0,1)
SB(0,1)
SSCG#
SDATA
IA(0:2)
Name
XOUT
VDDA
VDDB
AVDD
SCLK
OEA
OEB
VDD
REF
VSS
XIN
[3]
PWR
VDDA
VDDA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
–
–
–
–
–
[4]
PWR 3.3V common power supply pin for Bank A PCI clocks CLKA.
PWR 3.3V common power supply pin for Bank B PCI clocks CLKB.
PWR Power supply for internal Core logic.
PWR Power for internal analog circuitry. This supply should have a separately
PWR
I/O
I/O Data for the internal SMBus circuitry.
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Crystal Buffer input pin. Connects to a crystal, or an external clock source. Serves
as input clock TCLK, in Test mode.
Crystal Buffer output pin. Connects to a crystal only. When a Can Oscillator is used
or in Test mode, this pin is kept unconnected.
Buffered inverted outputs of the signal applied at Xin, typically 33.33 or 25.0 MHz
Output Enable for clock bank A. Causes the CLKA output clocks to be in a
three-state condition when driven to a logic low level.
Output Enable for clock bank B. Causes the CLKB output clocks to be in a
three-state condition when driven to a logic low level.
When this output signal is a logic low level, it indicates that the output clocks of the
A bank are locked to the input reference clock. This output is latched.
When this output signal is at a logic low level, it indicates that the output clocks of
the B bank are locked to the input reference clock. This output is latched.
Clock Bank A selection bits. These control the clock frequency that will be present
on the outputs of the A bank of buffers. See Table 1 for frequency codes and selection
values.
Clock Bank B selection bits. These control the clock frequency that will be present
on the outputs of the B bank of buffers. See Table 1 for frequency codes and selection
values.
SMBus address selection input pins. See Table 3 SMBus Address table.
Enables Spread Spectrum clock modulation when at a logic low level, see Spread
Spectrum Clocking on page 6.
Clock for the internal SMBus circuitry.
decoupled current source from VDD.
A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks.
A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks.
Ground pins for the device.
DD
pin. If these bypass capacitors are not close to the pins their high-frequency
Description
Page 2 of 11
C9530
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