LCDA15C-8 Semtech, LCDA15C-8 Datasheet - Page 4

LCDA15C-8

Manufacturer Part Number
LCDA15C-8
Description
Manufacturer
Semtech
Datasheet

Specifications of LCDA15C-8

Number Of Elements
8
Polarity
Bi-Directional
Package Type
SOIC
Operating Temperature Classification
Military
Reverse Breakdown Voltage
16.7V
Clamping Voltage
33V
Reverse Stand-off Voltage
15V
Leakage Current (max)
5uA
Peak Pulse Current
15A
Peak Pulse Power Dissipation
500W
Test Current (it)
1mA
Operating Temp Range
-55C to 125C
Mounting
Surface Mount
Pin Count
16
Lead Free Status / Rohs Status
Not Compliant

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Device Connection Options for Protection of Eight
High-Speed Data Lines
The LCDAxxC-8 may be configured to protect up to
eight I/O lines operating between 5 and 15V. It may be
used to protect the most popular serial data interface
standard lines making it ideal for use in equipment
utilizing multi-mode transceivers. The LCDAxxC-8 is
symmetrical so the data lines may be connected at
pins 1-8 or 9-16. Pins 9-16 or 1-8 are connected to
ground as shown. For best results, these pins should
be connected directly to a ground plane on the board.
The path length should be kept as short as possible to
minimize parasitic inductance.
Multi-Mode Transceiver Protection
The LCDAxxC-8 may be used to protect multi-mode
transceiver I/O lines with external connections. The
LCDAxxC-8 adds a maximum loading capacitance of
15pF with a working voltage of 12V or 15V. This allows
the transceiver to safely operate in all modes without
clipping or degradation of the signal.
With proper design and layout, the transceiver port can
be protected to >15kV (HBM per IEC 61000-4-2).
Circuit Board Layout Recommendations for Suppres-
sion of ESD.
Good circuit board layout is critical for the suppression
of fast rise-time transients such as ESD. The following
guidelines are recommended:
PROTECTION PRODUCTS
Applications Information
2005 Semtech Corp.
Place the LCDAxxC-8 near the input terminals or
connectors to restrict transient coupling.
Minimize the path length between the LCDAxxC-8
and the protected line.
Minimize all conductive loops including power and
ground loops.
The ESD transient return path to ground should be
kept as short as possible.
Never run critical signals near board edges.
Use ground planes whenever possible.
4
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small com-
pared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
LCDA12C-8 and LCDA15C-8
Device Connection
www.semtech.com

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