CY7C109B-15VCT Cypress Semiconductor Corp, CY7C109B-15VCT Datasheet - Page 3
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CY7C109B-15VCT
Manufacturer Part Number
CY7C109B-15VCT
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C109B-15VCT.pdf
(10 pages)
Specifications of CY7C109B-15VCT
Density
1Mb
Access Time (max)
15ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
17b
Package Type
SOJ
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
80mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Word Size
8b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant
Document #: 38-05038 Rev. *C
AC Test Loads and Waveforms
Switching Characteristics
OUTPUT
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
Notes:
Parameter
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
6. t
7. At any given temperature and voltage condition, t
8. The internal write time of the memory is defined by the overlap of CE
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
INCLUDING
JIG AND
SCOPE
I
write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the write.
OL
HZOE
5V
/I
OH
, t
HZCE
and 30-pF load capacitance.
30 pF
[8]
, and t
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE
CE
CE
CE
Write Cycle Time
CE
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
(a)
1
1
1
1
1
1
HZWE
HIGH to Power-Down, CE
LOW to Data Valid, CE
LOW to Low Z, CE
HIGH to High Z, CE
LOW to Power-Up, CE
LOW to Write End, CE
R1 480Ω
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
255Ω
R2
[9]
[5]
[7]
[6, 7]
[6, 7]
Description
OUTPUT
2
INCLUDING
JIG AND
SCOPE
2
HIGH to Low Z
LOW to High Z
5V
2
2
2
HZCE
HIGH to Write End
HIGH to Power-Up
HIGH to Data Valid
2
LOW to Power-Down
is less than t
5 pF
(b)
[7]
R1 480Ω
[6, 7]
LZCE
1
LOW, CE
, t
HZOE
Equivalent to:
is less than t
2
255Ω
HIGH, and WE LOW. CE
R2
Min.
7C1009B-12
7C109B-12
12
12
10
10
10
OUTPUT
3
0
3
0
0
0
7
0
3
GND
3.0V
LZOE
HZWE
≤ 3 ns
Max.
, and t
12
12
12
6
6
6
6
and t
THÉ
HZWE
SD
VENIN EQUIVALENT
1
.
167Ω
and WE must be LOW and CE
Min.
7C1009B-15
7C109B-15
15
15
12
12
12
is less than t
3
0
3
0
0
0
8
0
3
10%
90%
ALL INPUT PULSES
Max.
15
15
15
7
7
7
7
LZWE
1.73V
for any given device.
Min.
7C1009B-20
CY7C1009B
7C109B-20
20
20
15
15
12
10
3
0
3
0
0
0
0
3
CY7C109B
2
HIGH to initiate a
Max.
Page 3 of 10
20
20
20
8
8
8
8
90%
10%
≤ 3 ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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