CY7C1312AV18-133BZC Cypress Semiconductor Corp, CY7C1312AV18-133BZC Datasheet - Page 4

• Manufacturer Part Number: CY7C1312AV18-133BZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1312AV18-133BZC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Document #: 38-05497 Rev. *A
Pin Configurations
Pin Definitions
D
WPS
BWS
BWS
A
[x:0]
M
A
B
C
D
G
H
K
N
R
Pin Name
E
F
L
P
J
0
2
, BWS
, BWS
DOFF
TDO
D31
Q32
Q33
D33
D34
Q35
Q27
D27
D28
Q29
Q30
D30
1
3
CQ
,
1
V
SS
Synchronous
Synchronous
Synchronous
Synchronous
V
Q34
Q18
Q28
Q21
Q31
Q24
TCK
D20
D29
D22
D32
D26
D35
/288M NC/72M
REF
2
Input-
Input-
Input-
Input-
(continued)
I/O
V
D18
D19
Q19
Q20
D21
Q22
D23
Q23
D24
D25
Q25
Q26
DDQ
A
3
CY7C1314AV18 (512k × 36) – 11 × 15 BGA
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
CY7C1310AV18 - D
CY7C1312AV18 - D
CY7C1314AV18 - D
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When
asserted active, a write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D
Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and
K clocks during write operations. Used to select which byte is written into the device
during the current portion of the write operations. Bytes not written remain unaltered.
CY7C1310AV18 − BWS
CY7C1312AV18 − BWS
CY7C1314AV18 − BWS
and BWS
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte
Write Select will cause the corresponding byte of data to be ignored and not written into
the device.
Address Inputs. Sampled on the rising edge of the K (read address) and K (write
address) clocks during active read and write operations. These address inputs are multi-
plexed for both Read and Write operations. Internally, the device is organized as 2M x 8
(2 arrays each of 1M x 8) for CY7C1310AV18, 1M x 18 (2 arrays each of 512K x 18) for
CY7C1312AV18 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1314AV18.
Therefore, only 20 address inputs are needed to access the entire memory array of
CY7C1310AV18, 19 address inputs for CY7C1312AV18 and 18 address inputs for
CY7C1314AV18. These inputs are ignored when the appropriate port is deselected.
V
V
V
V
V
V
V
WPS
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
4
A
SS
SS
SS
SS
3
PRELIMINARY
controls D
BWS
BWS
V
V
V
V
V
V
V
V
V
5
A
A
A
A
DD
DD
DD
DD
DD
SS
SS
SS
SS
2
3
[7:0]
[17:0]
[35:0]
[35:27].
0
0
0
controls D
controls D
controls D
V
V
V
V
V
V
V
V
V
6
K
K
A
A
C
C
SS
SS
SS
SS
SS
SS
SS
SS
SS
Pin Description
[3:0]
[8:0]
[8:0]
BWS
BWS
V
V
V
V
V
V
V
V
V
7
A
A
A
A
DD
DD
DD
DD
DD
SS
SS
SS
SS
[x:0]
, BWS
and BWS
and BWS
1
0
to be ignored.
1
V
V
V
V
V
V
V
RPS
controls D
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
8
A
A
SS
SS
SS
SS
1
1
controls D
controls D
NC/36M V
VDDQ
[17:9]
D17
D16
Q16
Q15
D14
Q13
D12
Q12
D10
Q10
D11
Q9
A
9
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
[7:4]
[17:9].
, BWS
.
SS
V
TMS
2
Q17
D15
Q14
D13
Q11
Q7
D6
Q4
D3
Q1
D9
D0
10
/144M
REF
controls D
Page 4 of 21
TDI
CQ
Q8
Q6
Q5
ZQ
Q3
Q2
Q0
11
D8
D7
D5
D4
D2
D1
[26:18]