CY7C131-55JI Cypress Semiconductor Corp, CY7C131-55JI Datasheet

CY7C131-55JI

Manufacturer Part Number
CY7C131-55JI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C131-55JI

Density
8Kb
Access Time (max)
55ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
10b
Package Type
PLCC
Operating Temp Range
-40C to 85C
Number Of Ports
2
Supply Current
110mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
52
Word Size
8b
Number Of Words
1K
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C131-55JI
Manufacturer:
CYPRESS
Quantity:
8 831
Part Number:
CY7C131-55JI
Manufacturer:
CYP
Quantity:
475
Part Number:
CY7C131-55JI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Features
Cypress Semiconductor Corporation
Document #: 38-06002 Rev. *E
Logic Block Diagram
Notes
1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical.
2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor.
3. Open drain outputs: pull-up resistor required.
True dual-ported memory cells, which allow simultaneous
reads of the same memory location
1K x 8 organization
0.65 micron CMOS for optimum speed and power
High speed access: 15 ns
Low operating power: I
Fully asynchronous operation
Automatic power down
Master CY7C130/130A/CY7C131/131A easily expands data
bus width to 16 or more bits using slave CY7C140/CY7C141
BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY
input on CY7C140/CY7C141
INT flag for port-to-port communication
Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC,
52-pin TQFP
Pb-free packages available
CY7C140/CY7C141 (Slave): BUSY is input.
CC
BUSY
INT
R/W
I/O
I/O
CE
OE
A
= 110 mA (maximum)
A
L
L
7L
0L
[2]
9L
[3]
0L
L
L
L
DECODER
ADDRESS
R/W
198 Champion Court
CE
OE
L
L
L
CONTROL
I/O
(7C130/7C131 ONLY)
INTERRUPT LOGIC
ARBITRATION
MEMORY
ARRAY
LOGIC
AND
Functional Description
The CY7C130/130A/CY7C131/131A/CY7C140
are high speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/130A/ CY7C131/131A can be used as
either a standalone 8-bit dual-port static RAM or as a master
dual-port RAM in conjunction with the CY7C140/CY7C141 slave
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or multi-
processor designs.
Each port has independent control pins; chip enable (CE), write
enable (R/W), and output enable (OE). Two flags are provided
on each port, BUSY and INT. BUSY signals that the port is trying
to access the same location currently being accessed by the
other port. INT is an interrupt flag indicating that data is placed
in a unique location (3FF for the left port and 3FE for the right
port). An automatic power down feature is controlled indepen-
dently on each port by the chip enable (CE) pins.
The CY7C130/130A and CY7C140 are available in 48-pin DIP.
The CY7C131/131A and CY7C141 are available in 52-pin
PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free
PQFP.
1K x 8 Dual-Port Static RAM
CONTROL
I/O
San Jose
DECODER
ADDRESS
CE
OE
R/W
R
R
R
,
CA 95134-1709
CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
INT
A
A
R/W
CE
OE
I/O
I/O
BUSY
0R
9R
Revised December 09, 2008
R
7R
0R
R
R
R
[3]
R
[1]
and CY7C141
408-943-2600
[+] Feedback

Related parts for CY7C131-55JI

CY7C131-55JI Summary of contents

Page 1

... INT L Notes 1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical. 2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor. CY7C140/CY7C141 (Slave): BUSY is input. 3. Open drain outputs: pull-up resistor required. Cypress Semiconductor Corporation Document #: 38-06002 Rev. *E ...

Page 2

... Figure 1. Pin Diagram - DIP (Top View R BUSY R BUSY INT INT 7C130 7C140 I I I I/O 6R I/O I I/O I I/O I I I/O GND 0R Figure 3. Pin Diagram - PQFP (Top View 5150 I I 1415 CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 7C131 7C141 I Page [+] Feedback ...

Page 3

... Interrupt Flag Busy Flag Power Ground 7C130-30 7C130-35 [4] 7C130A-30 [4] 7C131-25 7C131-35 7C131-30 7C141-25 7C140-35 7C140-30 7C141-35 7C141- 190 170 170 CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Description 7C130-45 7C130-55 7C131-45 7C131-55 7C140-45 7C140-55 7C141-45 7C141- 120 120 110 Page Unit [+] Feedback ...

Page 4

... CC < 0.2V Com’l 125 L > V – 0.2V, CC > V – 0.2V CC < 0.2V, IN [11] and using AC Test Waveforms input levels of GND to 3V. RC CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Ambient Temperature V CC ° ° + ± 10% ° ° – + ± 10% ° ° –55 ...

Page 5

... Figure 4. AC Test Loads and Waveforms R1 893Ω 5V OUTPUT 347Ω INCLUDING JIGAND SCOPE (b) ALL INPUT PULSES 3.0V 90% 10% GND 1.40V ≤ CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Max Unit 281Ω BUSY OR INT 30 pF BUSY Output Load (CY7C130/CY7C131 ONLY) 90% 10% ≤5ns Page [+] Feedback ...

Page 6

... Min Max [10 less than t and t HZCE LZCE HZOE = part ( Test Loads. Transition is measured ±500 mV from steady state voltage. L CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 7C130-30 [4] 7C130-25 7C130A-30 7C131-25 7C131-30 7C140-25 Unit 7C140-30 7C141-25 7C141-30 Min Max Min Max ...

Page 7

... R/W for Port B is toggled during valid read. Document #: 38-06002 Rev. *E [7, 12] (continued) [4] 7C131-15 7C131A-15 7C141-15 Min Max 15 [17 [17 Note 19 Note [17] 15 [17] 15 [17] 15 CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 7C130-30 [4] 7C130-25 7C130A-30 7C131-25 7C131-30 7C140-25 Unit 7C140-30 7C141-25 7C141-30 Min Max Min Max ...

Page 8

... EINR t Address to INTERRUPT Reset Time INR Document #: 38-06002 Rev. *E [7,12] 7C130-35 7C131-35 7C140-35 7C141-35 Min Max [10 [17 [17 Note 19 Note [17] 25 [17] 25 [17] 25 CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 7C130-45 7C130-55 7C131-45 7C131-55 7C140-45 7C140-55 Unit 7C141-45 7C141-55 Min Max Min Max ...

Page 9

... Switching Waveforms ADDRESS t OHA DATA OUT PREVIOUS DATA VALID LZOE t LZCE DATA OUT Read with BUSY, Master: CY7C130 and CY7C131 ADDRESS R R INR ADDRESS BUSY L DOUT L Notes 20. R/W is HIGH for read cycle. 21. Device is continuously selected and 22. Address valid prior to or coincident with CE transition LOW. ...

Page 10

... Document #: 38-06002 Rev. *E Either Port SCE PWE t SD DATA VALID HIGH IMPEDANCE SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE PWE HZWE CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 [16, 23 [17, 24 LZWE to allow the data I/O pins to enter high impedance Page [+] Feedback ...

Page 11

... PS ADDRESS R BUSY R Right Address Valid First ADDRESS MATCH ADDRESS ADDRESS L BUSY L Document #: 38-06002 Rev. *E ADDRESS MATCH BLC BHC ADDRESS MATCH BLC BHC ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Page [+] Feedback ...

Page 12

... Switching Waveforms (continued) Write with BUSY (Slave:CY7C140/CY7C141 BUSY Document #: 38-06002 Rev. *E Figure 12. Busy Timing Diagram No PWE t WH CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Page [+] Feedback ...

Page 13

... INT L Left Side Clears INT L ADDR R INT L Document #: 38-06002 Rev. *E Figure 13. Interrupt Timing Diagrams t WC WRITE 3FF EINS t WINS INT t EINR t OINR EINS t WINS EINR CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 t RC READ 3FF t RC READ 3FE INR t OINR Page [+] Feedback ...

Page 14

... OUTPUT LOADING 30.0 25.0 20.0 15.0 10 4. 25° 200 400 600 800 1000 CAPACITANCE (pF) CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 5. 25° 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE ...

Page 15

... CY7C131-30JI 35 CY7C131-35JC CY7C131-35NC CY7C131-35JI CY7C131-35NI 45 CY7C131-45JC CY7C131-45NC CY7C131-45JI CY7C131-45NI 55 CY7C131-55JC CY7C131-55JXC CY7C131-55NC CY7C131-55NXC CY7C131-55JI CY7C131-55JXI CY7C131-55NI CY7C131-55NXI 30 CY7C140-30PC CY7C140-30PI Document #: 38-06002 Rev. *E Package Package Type Name P25 48-Pin (600 Mil) Molded DIP P25 48-Pin Pb-Free (600 Mil) Molded DIP P25 48-Pin (600 Mil) Molded DIP ...

Page 16

... Plastic Quad Flatpack J69 52-Pin Plastic Leaded Chip Carrier N52 52-Pin Plastic Quad Flatpack J69 52-Pin Plastic Leaded Chip Carrier N52 52-Pin Plastic Quad Flatpack CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial ...

Page 17

... Figure 14. 48-Pin (600 Mil) Sidebraze DIP D26 MIL-STD-1835 D-14 Config. C SEATING PLANE 0.045 0.055 34 0.023 0.033 33 0.750 0.756 0.785 0.795 CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 51-80044 ** MIN. DIMENSIONS IN INCHES MAX. 0.013 0.021 0.690 0.730 0.020 MIN. 0.090 0.130 0.165 0.200 51-85004-*A Page ...

Page 18

... Package Diagrams (continued) Figure 17. 52-Pin Pb-Free Plastic Quad Flatpack N52 Document #: 38-06002 Rev. *E Figure 16. 48-Pin (600 Mil) Molded DIP P25 CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 51-85020-*B 51-85042-** Page [+] Feedback ...

Page 19

... Document History Page Document Title: CY7C130/CY7C130A/CY7C131/CY7C131A/CY7C140/CY7C141 Dual-Port Static RAM Document Number: 38-06002 Orig. of Rev. ECN No. Change ** 110169 SZV *A 122255 RBI *B 236751 YDT *C 325936 RUY *D 393153 YIM *E 2623540 VKN/PYRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...

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