CY7C1347B-166BGC Cypress Semiconductor Corp, CY7C1347B-166BGC Datasheet
CY7C1347B-166BGC
Specifications of CY7C1347B-166BGC
Related parts for CY7C1347B-166BGC
CY7C1347B-166BGC Summary of contents
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... Pentium and Intel are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. Cypress Semiconductor Corporation The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when V All synchronous inputs pass through input registers controlled by the rising edge of the clock ...
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... Pin Configurations DDQ V SSQ BYTE2 SSQ V DDQ DDQ V SSQ BYTE3 SSQ V DDQ 100-Pin TQFP CY7C1347B CY7C1347B DDQ V 76 SSQ BYTE1 SSQ 70 V DDQ DDQ 60 V SSQ BYTE0 SSQ 54 V DDQ ...
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... Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) 119-Ball BGA ADSP CE A ADSC DQP ADV CLK BWE DQP MODE 7C1347B-166 3.5 420 10 3 CY7C1347B DDQ DQP DDQ DDQ DDQ DQP DDQ 7C1347B-133 7C1347B-100 4.0 5.5 375 325 ...
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... When ADSP and [1:0] are also loaded into the burst counter. When ADSP and [1:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by 4 CY7C1347B , and CE are sampled active. A feed the 2 3 [1:0] and BWE) ...
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... Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1347B is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ [31:0] output drivers safety precaution, DQ automatically three-stated whenever a write cycle is detected, regardless of the state of OE ...
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... ADSP , and ADSC must remain inactive for the duration of t ZZREC 00 Fourth Address A [1: Test Conditions Min. ZZ > > < 0.2V 2t CYC 6 CY7C1347B after the ZZ input returns LOW. Max. Unit CYC ns ...
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... The DQ pins are controlled by the current cycle and the OE signal asynchronous and is not sampled with the clock ADSP ADSC CY7C1347B ADV OE DQ Write Hi-Z Read Hi-Z Read Read Hi-Z Read Read Hi-Z Read Read Hi-Z Read Read Hi-Z Write Hi-Z Write Hi-Z Write Hi-Z Write 1 0 ...
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... X Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 +150 C Operating Range +125 C 0.5V to +4.6V Range Temperature Com’ + 0. 0.5V Ind’l – + ;DP = data when OE is active. [31:0] [3:0] 8 CY7C1347B ...
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... MHz > V – 0. DDQ 7.5-ns cycle, 133 MHz 1/t MAX CYC 10-ns cycle, 100 MHz Max Device Deselected Test Conditions MHz 3.3V 3.3V DDQ 9 CY7C1347B Min. Max. Unit 3.135 3.6 V 2.375 3.6 V 2.4 V 0.4 V 2 –0.3 0 – – 420 mA ...
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... EOLZ CHZ CLZ 10 CY7C1347B [10] ALL INPUT PULSES 90% 90% 10% 10% 2.5 ns 2.5 ns (c) -133 -100 Min. Max. Min. Max. 7.5 10 1.9 3.5 1.9 3.5 1 ...
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... GW to define a write cycle (see Write Cycle Description table). [3:0] 15. WDx stands for Write Data to Address X. Burst Write ADSP ignored with WD2 masks ADSP UNDEFINED = DON’T CARE 11 CY7C1347B Pipelined Write Unselected inactive ADSC initiated write WD3 Unselected with CE 2 High ...
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... CO Data Out 1a 1a Note: 16. RDx stands for Read Data from Address X. Burst Read ADSP ignored with Suspend Burst ADH masks ADSP OEHZ t DOH CLZ = DON’T CARE = UNDEFINED 12 CY7C1347B Unselected Pipelined Read inactive 1 ADSC initiated read RD3 Unselected with CHZ ...
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... Note: 17. Data bus is driven by SRAM, but data is not guaranteed. Single Write Burst Read CH t ADSP ignored with ADH RD3 masks ADSP EOHZ t DS See Note Out Out In = DON’T CARE = UNDEFINED 13 CY7C1347B Unselected Pipelined Read inactive DOH Out Out Out t CHZ ...
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... Back to Back Reads Notes: 18. Device originally deselected. 19 the combination of CE and CE . All chip selects need to be active in order to select the device CYC CH WD1 t ADH t CEH t WES ADSP ignored with CE HIGH Out Out In = DON’T CARE = UNDEFINED 14 CY7C1347B CL WD2 WD3 WD4 t WEH D( DOH t CHZ ...
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... CLK ADSP HIGH ADSC CE 1 LOW CE 2 HIGH I/Os Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 21. I/Os are in three-state when exiting ZZ sleep mode. t ZZS I (active DDZZ Three-state 15 CY7C1347B t ZZREC ...
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... Ordering Information Speed (MHz) Ordering Code 166 CY7C1347B-166AC CY7C1347B-166BGC 133 CY7C1347B-133AC CY7C1347B-133BGC CY7C1347B-133AI CY7C1347B-133BGI 100 CY7C1347B-100AC CY7C1347B-100BGC CY7C1347B-100AI CY7C1347B-100BGI Document #: 38-00909-*D Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Package Name Package Type A101 100-Lead Thin Quad Flat Pack BG119 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead FBGA ( 2.4 mm) BG119 CY7C1347B 51-85115 ...