CY7C235A-40DMB Cypress Semiconductor Corp, CY7C235A-40DMB Datasheet - Page 3

• Manufacturer Part Number: CY7C235A-40DMB
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C235A-40DMB

• Density: 8Kb
• Supply Current: 120mA
• Pin Count: 24
• Mounting: Through Hole
• Operating Temperature Classification: Military
• Lead Free Status / Rohs Status: Not Compliant

a
AC Test Loads and Waveforms
Operating Modes
The CY7C235A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with synchronous (E
enables and asynchronous initialization (INIT).
Upon power-up, the synchronous enable (ES) flip-flop will be
in the set condition causing the outputs (O
OFF or high-impedance state. Data is read by applying the
memory location to the address input (A
to the enable (E
loaded into the master flip-flops of the data register during the
address set-up time. At the next LOW-to-HIGH transition of the
clock (CP), data is transferred to the slave flip-flops, which
drive the output buffers, and the accessed data will appear at
the outputs (O
also LOW.
The outputs may be disabled at any time by switching the
asynchronous enable (E) to a logic HIGH, and may be
returned to the active state by switching the enable to a logic
LOW.
Regardless of the condition of E, the outputs will go to the OFF
or high-impedance state upon the next positive clock edge
after the synchronous enable (E
level. If the synchronous enable pin is switched to a logic LOW,
the subsequent positive clock edge will return the output to the
active state if E is LOW. Following a positive clock edge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
LOW-to-HIGH transition of the clock. This unique feature
allows the CY7C235A decoders and sense amplifiers to
access the next location while previously addressed data
remains stable on the outputs.
Document #: 38-04002 Rev. *B
OUTPUT
Equivalent to:
INCLUDING
5V
(a) NormalLoad
JIG AND
SCOPE
50 pF
OUTPUT
0
O
S
7
) input. The stored data is accessed and
), provided the asynchronous enable (E) is
R1 250
TH ÉVENIN EQUIVALENT
R2
167
100
S
) and asynchronous (E) output
S
) input is switched to a HIGH
OUTPUT
INCLUDING
5V
0
[5]
JIG AND
A
(b) High -ZLoad
2.0V
SCOPE
9
0
) and a logic LOW
5 pF
O
7
) to be in the
R1 250
R2
167
System timing is simplified in that the on-chip edge-triggered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
The CY7C235A has an asynchronous initialize input (INIT).
The initialize function is useful during power-up and time-out
sequences and can facilitate implementation of other sophis-
ticated functions such as a built-in “jump start” address. When
activated the initialize control input causes the contents of a
user programmed 1025th 8-bit word to be loaded into the
on-chip register. Each bit is programmable and the initialize
function can be used to load any desired combination of 1s
and 0s into the register. In the unprogrammed state, activating
INIT will generate a register CLEAR (all outputs LOW). If all
the bits of the initialize word are programmed, activating INIT
performs a register PRESET (all outputs HIGH).
Applying a LOW to the INIT input causes an immediate load
of the programmed initialize word into the master and slave
flip-flops of the register, independent of all other inputs,
including the clock (CP). The initialize data will appear at the
device outputs after the outputs are enabled by bringing the
asynchronous enable (E) LOW.
When power is applied the (internal) synchronous enable
flip-flop will be in a state such that the outputs will be in the
high-impedance state. In order to enable the outputs, a clock
must occur and the ES input pin must be LOW at least a set-up
time prior to the clock LOW-to-HIGH transition. The E input
may then be used to enable the outputs.
When the asynchronous initialize input, INIT, is LOW, the data
in the initialize byte will be asynchronously loaded into the
output register. It will not, however, appear on the output pins
until they are enabled, as described in the preceding
paragraph.
GND
3.0V
5 ns
10%
ALL INPUT PULSES
90%
CY7C235A
90%
Page 3 of 10
10%
5 ns
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