CY7C109-15VCT Cypress Semiconductor Corp, CY7C109-15VCT Datasheet - Page 4

• Manufacturer Part Number: CY7C109-15VCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C109-15VCT

• Density: 1Mb
• Access Time (max): 15ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 17b
• Package Type: SOJ
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 155mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05032 Rev. **
Switching Characteristics
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Shaded areas contain preliminary information.
Notes:
Parameter
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
5.
6.
7.
8.
9.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
t
At any given temperature and voltage condition, t
The internal write time of the memory is defined by the overlap of CE
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
OL
HZOE
/I
OH
, t
and 30-pF load capacitance.
HZCE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE
CE
CE
Power-Up
CE
Power-Down
Write Cycle Time
CE
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
, and t
[8,9]
1
1
1
1
1
1
LOW to Write End, CE
HZWE
LOW to Data Valid, CE
LOW to Low Z, CE
HIGH to High Z, CE
LOW to Power-Up, CE
HIGH to Power-Down, CE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
Description
[7]
[6, 7]
[6, 7]
[3, 5]
2
Over the Operating Range
2
HIGH to Low Z
LOW to High Z
2
2
2
HIGH to Write End
HIGH to
HIGH to Data
HZCE
2
LOW to
is less than t
[7]
[6, 7]
LZCE
1
, t
LOW, CE
HZOE
Min.
10
10
7C1009-10
3
0
3
0
8
8
0
0
8
6
0
3
is less than t
7C109-10
2
HIGH, and WE LOW. CE
Max.
LZOE
10
10
10
5
5
5
5
, and t
HZWE
HZWE
and T
Min.
12
12
10
10
10
7C1009-12
3
0
3
0
0
0
7
0
3
7C109-12
is less than t
1
SD
and WE must be LOW and CE
.
Max.
12
12
12
6
6
6
6
LZWE
for any given device.
Min.
15
15
12
12
12
7C1009-15
3
0
3
0
0
0
8
0
3
7C109-15
2
HIGH to initiate a write,
CY7C1009
Max.
CY7C109
15
15
15
7
7
7
7
Page 4 of 12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns