CAT25C64S-TE13 ON Semiconductor, CAT25C64S-TE13 Datasheet - Page 5

• Manufacturer Part Number: CAT25C64S-TE13
• Manufacturer: ON Semiconductor

Specifications of CAT25C64S-TE13

• Density: 64Kb
• Interface Type: Serial (SPI)
• Organization: 8Kx8
• Access Time (max): 250ns
• Frequency (max): 3MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: SOIC
• Operating Temp Range: 0C to 70C
• Supply Current: 10mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Not Compliant

CS
CS
WP
WP
STATUS REGISTER
the communication between the microcontroller and the
25C32/64. Opcodes, byte addresses, or data present on
the SI pin are latched on the rising edge of the SCK. Data
on the SO pin is updated on the falling edge of the SCK.
CS
CS: Chip Select
CS
CS is the Chip select pin. CS low enables the CAT25C32/
64 and CS high disables the CAT25C32/64. CS high
takes the SO output pin to high impedance and forces
the devices into a Standby Mode (unless an internal
write operation is underway). The CAT25C32/64 draws
ZERO current in the Standby mode. A high to low
transition on CS is required prior to any sequence being
initiated. A low to high transition on CS after a valid write
sequence is what initiates an internal write cycle.
WP
WP
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
BLOCK PROTECTION BITS
WRITE PROTECT ENABLE OPERATION
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
WPEN
WPEN
X
X
0
0
1
1
BP1
7
0
0
1
1
Status Register Bits
High
High
Low
Low
WP
WP
WP
WP
WP
X
6
X
X
BP0
0
1
0
1
X
5
WEL
0
1
0
1
0
1
25C32: 0C00-0FFF
25C32: 0000-0FFF
X
4
25C64:1800-1FFF
25C32: 800-0FFF
25C64:1000-1FFF
25C64:0000-1FFF
Array Address
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Blocks
None
5
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register. The WP pin function is blocked when the WPEN
bit is set to 0.
HOLD
HOLD
HOLD: Hold
The HOLD pin is used to pause transmission to the
CAT25C32/64 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause, HOLD must be brought low while SCK
is low. The SO pin is in a high impedance state during the
time the part is paused, and transitions on the SI pins will
be ignored. To resume communication, HOLD is brought
high, while SCK is low. (HOLD should be held high any
time this function is not being used.) HOLD may be tied
high directly to V
Figure 9 illustrates hold timing sequence.
HOLD
HOLD
BP1
3
Unprotected
Protected
Protected
Protected
BP0
Writable
Writable
Writable
Blocks
2
cc
or tied to V
Quarter Array Protection
Half Array Protection
Full Array Protection
No Protection
WEL
Protection
1
cc
through a resistor.
Protected
Protected
Protected
Protected
Register
Writable
Writable
CAT25C32/64
Status
Doc. No. 1001, Rev. J
RDY
0