EPM9320RI208-20 Altera, EPM9320RI208-20 Datasheet - Page 8

• Manufacturer Part Number: EPM9320RI208-20
• Manufacturer: Altera

Specifications of EPM9320RI208-20

• Family Name: MAX 9000
• Memory Type: EEPROM
• # Macrocells: 320
• Number Of Usable Gates: 6000
• Frequency (max): 100MHz
• Propagation Delay Time: 23ns
• Number Of Logic Blocks/elements: 20
• # I/os (max): 132
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: RQFP
• Lead Free Status / Rohs Status: Not Compliant

MAX 9000 Programmable Logic Device Family Data Sheet
Figure 3. MAX 9000 Macrocell & Local Array
8
33 Row
FastTrack
Interconnect
Inputs
16 Local
Feedbacks
LAB Local
Array
Macrocells
The MAX 9000 macrocell consists of three functional blocks: the product
terms, the product-term select matrix, and the programmable register.
The macrocell can be individually configured for both sequential and
combinatorial logic operation. See
Combinatorial logic is implemented in the local array, which provides five
product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register clear, preset, clock, and clock enable control
functions. Two kinds of expander product terms (“expanders”) are
available to supplement macrocell logic resources:
The MAX+PLUS II software automatically optimizes product-term
allocation according to the logic requirements of the design.
16 Shareable
Expander Product
Shareable expanders, which are inverted product terms that are fed
back into the logic array
Parallel expanders, which are product terms borrowed from adjacent
macrocells
Product-
Select
Matrix
Term
Parallel
Expanders
(from Other
Macrocells)
Global
Clear
Select
Clear
Figure
Clocks
Global
2
VCC
Enable
Clock/
Select
Macrocell
Input Select
3.
Register
Bypass
ENA
D/T
CLRN
PRN
Q
Altera Corporation
Programmable
Register
To Row or
Column
FastTrack
Interconnect
Local Array
Feedback