LM80CIMTX-3 National Semiconductor, LM80CIMTX-3 Datasheet - Page 20

• Manufacturer Part Number: LM80CIMTX-3
• Manufacturer: National Semiconductor

Specifications of LM80CIMTX-3

• Battery Backup Switching: No
• Watchdog Timer: Yes
• Chip Enable Signals: No
• Manual Reset: No
• Package Type: TSSOP
• Operating Supply Voltage (min): 2.8V
• Operating Supply Voltage (max): 5.75V
• Operating Temp Range: -25C to 125C
• Operating Temperature Classification: Commercial
• Power Fail Detection: No
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / Rohs Status: Not Compliant

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8.2 Interrupt Outputs
All Interrupts are indicated in the two Interrupt Status Regis-
ters.
8.3 Interrupt Clearing
Reading an Interrupt Status Register will output the contents
of the Register, and reset the Register. A subsequent read
done before the analog “round-robin” monitoring loop is com-
plete will indicate a cleared Register. Allow at least 1.5 sec-
onds to allow all Registers to be updated between reads. In
summary, the Interrupt Status Register clears upon being
read, and requires at least 1.5 seconds to be updated. When
the Interrupt Status Register clears, the hardwire interrupt line
will also clear until the Registers are updated by the monitor-
ing loop. The hardware Interrupt lines are cleared with the
INT_Clear bit, which is Bit 3 of the Configuration Register,
without affecting the contents of the Interrupt (INT) Status
Registers. When this bit is high, the LM80 monitoring loop will
stop. It will resume when the bit is low.
9.0 RST and GPO OUTPUTS
In PC applications the open drain GPO provides a gate drive
signal to an external P-channel MOSFET power switch. This
external MOSFET then would keep power turned on regard-
less of the state of front panel power switches when software
power control is used. In any given application this signal is
not limited to the function described by its label. For example,
since the LM80 incorporates temperature sensing, the GPO
output could also be utilized to control power to a cooling fan.
Take GPO active low by setting Bit 6 in the Configuration
Register low.
RST is intended to provide a master reset to devices con-
nected to this line. The RST_OUT/OS Control bit in Fan
Divisor/RST_OUT/OS Register, Bit 7, must be set high to en-
able this function. Setting Bit 4 in the Configuration Register
high outputs a least 10 ms low on this line, at the end of which
Bit 4 in the Configuration Register automatically clears. Again,
the label for this pin is only its suggested use. In applications
where the RST capability is not needed it can be used for any
type of digital control that requires a 10 ms active low open
drain output.
INT output has two mask registers, and individual masks
for each Interrupt. As described in Section 3.3, this
hardware Interrupt line can also be enabled/disabled in the
Configuration Register. The Configuration Register is also
used to set the mode of the INT Interrupt line.
OS is dedicated to the Temperature reading
WATCHDOG. In the “Fan Divisor/RST_OUT/OS Register”
the OS enable bit (Bit-6), must be set high and the RST
enable bit (Bit -7) must be set low to enable the OS function
on the RST_OUT/OS pin. OS pin has two modes of
operation: “One-Time Interrupt” and “Comparator”. “One-
Time Interrupt” mode is selected by taking bit-2 of the
“OS Configuration/Temperature Resolution Register”
high. If bit-2 is taken low “Comparator” mode is selected.
Unlike the OS pin, the OS bit in “Interrupt Status Register
2” functions in “Default Interrupt” and “One-Time Interrupt”
modes. The OS bit can be masked to INT pin by taking
bit-5 in the “Interrupt Mask Register 2” low. A description
of “Comparator”, “Default Interrupt” and “One-Time
Interrupt” modes can be found in Section 7.1.
20
10.0 NAND TREE TESTS
A NAND tree is provided in the LM80 for Automated Test
Equipment (ATE) board level connectivity testing. If the user
applies a logic zero to the NTEST_IN/Reset_IN input pin, the
device will be in the NAND tree test mode. A0/NTEST_OUT
will become the NAND tree output pin. To perform a NAND
tree test all pins included in the NAND tree should be driven
to 1. Beginning with IN0 and working clockwise around the
chip, each pin can be toggled and a resulting toggle can be
observed on A0/NTEST_OUT. The following pins are exclud-
ed from the NAND tree test: GNDA (analog ground), GND
(digital ground), V + (power supply), A0/NTEST_OUT,
NTEST_IN/Reset_IN and RST_OUT/OS. Allow for a typical
propagation delay of 500 ns.
11.0 FAN MANUFACTURERS
Manufacturers of cooling fans with tachometer outputs are
listed below:
NMB Tech
9730 Independence Ave.
Chatsworth, California 91311
818 341-3355
818 341-8207
Mechatronics Inc.
P.O. Box 20
Mercer Island, WA 98040
800 453-45698
Various sizes available with tach output option.
Sanyo Denki America, Inc.
468 Amapola Ave.
Torrance, CA 90501
310 783-5400
Model Number
109P06XXY601
109R06XXY401
109P08XXY601
109R08XXY401
Model Number
2408NL
2410ML
3108NL
3110KL
(60 mm sq. X 20 mm)
(60 mm sq. X 25 mm)
(80 mm sq. X 20 mm)
(80 mm sq. X 25 mm)
2.36 in sq. X 0.79 in
2.36 in sq. X 0.98 in
3.15 in sq. X 0.79 in
3.15 in sq. X 0.98 in
(60 mm sq. X 20 mm)
(60 mm sq. X 25 mm)
(80 mm sq. X 20 mm)
(80 mm sq. X 25 mm)
2.36 in sq. X 0.79 in
2.36 in sq. X 0.98 in
3.15 in sq. X 0.79 in
3.15 in sq. X 0.98 in
Frame Size
Frame Size
Airflow CFM
14-25
25-42
25-40
9-16
Airflow
11-15
13-28
23-30
21-42
CFM