AT49LV002-70JC Atmel, AT49LV002-70JC Datasheet - Page 11
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AT49LV002-70JC
Manufacturer Part Number
AT49LV002-70JC
Description
Manufacturer
Atmel
Datasheet
1.AT49LV002-70JC.pdf
(26 pages)
Specifications of AT49LV002-70JC
Cell Type
NOR
Density
2Mb
Access Time (max)
70ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
18b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
PLCC
Program/erase Volt (typ)
3 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
256K
Supply Current
25mA
Mounting
Surface Mount
Pin Count
32
Lead Free Status / Rohs Status
Not Compliant
Program Cycle Characteristics
Program Cycle Waveforms
Sector or Chip Erase Cycle Waveforms
Notes:
0982D–FLASH–02/03
Symbol
t
t
t
t
t
t
t
t
BP
AS
AH
DS
DH
WP
WPH
EC
1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased.
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
(See note 4 under command definitions.)
Parameter
Byte Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
A0 - A17
A0 - A17
DATA
WE
OE
CE
(1)
t
AS
5555
t
BYTE 0
AH
AA
t
t
DS
WP
2AAA
t
BYTE 1
DH
55
5555
t
WPH
BYTE 2
80
5555
BYTE 3
AA
2AAA
Min
70
70
90
90
0
0
BYTE 4
55
AT49BV/LV002(N)(T)
Note 2
BYTE 5
Note 3
Typ
30
t
EC
Max
50
10
seconds
Units
µs
ns
ns
ns
ns
ns
ns
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