M24256-WMW6T STMicroelectronics, M24256-WMW6T Datasheet - Page 16
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M24256-WMW6T
Manufacturer Part Number
M24256-WMW6T
Description
Manufacturer
STMicroelectronics
Datasheet
1.M24256-WMW6T.pdf
(39 pages)
Specifications of M24256-WMW6T
Density
256Kb
Interface Type
Serial (I2C)
Organization
32Kx8
Access Time (max)
900ns
Frequency (max)
400KHz
Write Protection
Yes
Data Retention
40Year
Operating Supply Voltage (typ)
3.3/5V
Package Type
SOIC
Operating Temp Range
-40C to 85C
Supply Current
1mA
Operating Supply Voltage (min)
2.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M24256-WMW6T
Manufacturer:
ST
Quantity:
20 000
Device operation
4.6
4.7
4.8
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Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data Byte.
Writing to the memory may be inhibited if Write Control (WC) is driven high. Any Write
instruction with Write Control (WC) driven high (during a period of time from the Start
condition until the end of the two address bytes) will not modify the memory contents, and
the accompanying data bytes are not acknowledged, as shown in
Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant
Byte
form the address of the byte in memory.
When the bus master generates a Stop condition immediately after the Ack bit (in the “10
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is
triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.
After the Stop condition, the delay t
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in
Page Write
The Page Write mode allows up to 32 bytes (for the M24C32 and M24C64) or 64 bytes (for
the M24128) to be written in a single Write cycle, provided that they are all located in the
same ‘row’ in the memory: that is, the most significant memory address bits (b13-b6 for
M24128, b12-b5 for M24C64, and b11-b5 for M24C32) are the same. If more bytes are sent
than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. This should be
avoided, as data starts to become overwritten in an implementation dependent way.
The bus master sends from 1 to 32 bytes of data (for the M24C32 and M24C64) or 64 bytes
of data (for the M24128), each of which is acknowledged by the device if Write Control (WC)
is low. If Write Control (WC) is high, the contents of the addressed memory location are not
modified, and each data byte is followed by a NoAck. After each byte is transferred, the
internal byte address counter (inside the page) is incremented. The transfer is terminated by
the bus master generating a Stop condition.
(Table
4) is sent first, followed by the Least Significant Byte
W
, and the successful completion of a Write operation,
Figure
9.
Figure
M24128, M24C64, M24C32
(Table
Figure
9, and waits for two
5). Bits b15 to b0
8.
th