IDT71V428S12Y IDT, Integrated Device Technology Inc, IDT71V428S12Y Datasheet

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IDT71V428S12Y

Manufacturer Part Number
IDT71V428S12Y
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT71V428S12Y

Density
4Mb
Access Time (max)
12ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
20b
Package Type
SOJ
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
140mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Word Size
4b
Number Of Words
1M
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT71V428S12Y
Manufacturer:
IDT
Quantity:
3 000
Part Number:
IDT71V428S12Y
Manufacturer:
IDT
Quantity:
20 000
Part Number:
IDT71V428S12YI
Manufacturer:
IDT
Quantity:
3 000
Features
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Functional Block Diagram
©2004 Integrated Device Technology, Inc.
1M x 4 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise
Equal access and cycle times
— Commercial and Industrial: 10/12/15ns
Single 3.3V power supply
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
LVTTL-compatible
Low power consumption via chip deselect
Available in 32-pin, 400 mil plastic SOJ package.
I/O
0
– I/O
A
A
19
3
0
WE
OE
CS
4
3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
ADDRESS
DECODER
4
CONTROL
LOGIC
1
Description
nized as 1M x 4. It is fabricated using IDT’s high-perfomance, high-
reliability CMOS technology. This state-of-the-art technology, com-
bined with innovative circuit design techniques, provides a cost-
effective solution for high-speed memory needs.
5ns, with address access times as fast as 10ns. All bidirectional inputs
and outputs of the IDT71V428 are LVTTL-compatible and operation is
from a single 3.3V supply. Fully static asynchronous circuitry is used,
requiring no clocks or refresh for operation.
The IDT71V428 is a 4,194,304-bit high-speed Static RAM orga-
The IDT71V428 has an output enable pin which operates as fast as
The IDT71V428 is packaged in a 32-pin, 400 mil Plastic SOJ.
MEMORY ARRAY
I/O CONTROL
4,194,304-BIT
SEPTEMBER 2004
IDT71V428S
IDT71V428L
3623 drw 01
4
DSC-3623/06

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IDT71V428S12Y Summary of contents

Page 1

Features ◆ ◆ ◆ ◆ ◆ advanced high-speed CMOS Static RAM ◆ ◆ ◆ ◆ ◆ JEDEC Center Power / GND pinout for reduced noise ◆ ◆ ◆ ◆ ◆ Equal access and cycle times — Commercial ...

Page 2

IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) Pin Configuration I SO32 ...

Page 3

IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) Absolute Maximum Ratings Symbol Rating V Supply Voltage Relative Terminal Voltage Relative IN OUT Temperature Under Bias BIAS ...

Page 4

IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load AC Test Loads +1.5V I 50Ω 0 Figure ...

Page 5

IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) AC Electrical Characteristics Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Select Access Time ACS (1) t Chip Select to Output in ...

Page 6

IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) Timing Waveform of Read Cycle No. 1 ADDRESS OE CS DATA OUT SUPPLY DD CURRENT I SB Timing Waveform of Read Cycle No. 2 ADDRESS PREVIOUS ...

Page 7

IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) Timing Waveform of Write Cycle No.1 (WE Controlled Timing) ADDRESS DATA (3) OUT DATA IN Timing Waveform of Write Cycle No.2 (CS Controlled Timing) ADDRESS ...

Page 8

IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) Ordering Information IDT X 71V428 X XX Die Device Power Speed Type Revision X XXX X Package Process/ Temperature Range Blank 10 Commercial ...

Page 9

IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM 4 Meg (1M x 4-Bit) Datasheet Document History 8/31/99 Updated to new format Pg. 2 Added footnote for V Pg. 4 Added footnote on jig and scope capacitance in Figure 2 Pg. 7 Revised ...

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