70V261L25PFG IDT, Integrated Device Technology Inc, 70V261L25PFG Datasheet

70V261L25PFG

Manufacturer Part Number
70V261L25PFG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of 70V261L25PFG

Density
256Kb
Access Time (max)
25ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
14b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
140mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
16b
Number Of Words
16K
Lead Free Status / Rohs Status
Compliant
Features
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
©2009 Integrated Device Technology, Inc.
Functional Block Diagram
I/O
I/O
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 25/35/55ns (max.)
– Industrial: 25ns (max.)
Low-power operation
– IDT70V261S
– IDT70V261L
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
8L
0L
BUSY
-I/O
Active: 300mW (typ.)
Standby: 3.3mW (typ.)
Active: 300mW (typ.)
Standby: 660 µ W (typ.)
-I/O
SEM
R/W
A
INT
UB
CE
OE
LB
A
15L
13L
7L
0L
L
L
L
L
L
L
L
L
(1,2)
(2)
Decoder
Address
R/W
OE
CE
L
L
L
14
Control
HIGH-SPEED 3.3V
16K x 16 DUAL-PORT
STATIC RAM
I/O
ARBITRATION
SEMAPHORE
INTERRUPT
MEMORY
ARRAY
LOGIC
M/S
1
IDT70V261 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
M/S = V
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP, Thin Quad Plastic Flatpack
Industrial temperature range (-40°C to +85°C) is available
for selected speed
Green parts available, see ordering information
Control
IH
IL
I/O
for BUSY input on Slave
for BUSY output flag on Master
14
Decoder
Address
CE
OE
R/W
R
R
R
JANUARY 2009
IDT70V261S/L
3040 drw 01
I/O
R/W
UB
I/O
BUSY
A
A
SEM
INT
OE
LB
CE
13R
0R
DSC-3040/10
8R
R
0R
R
R
R
R
R
R
(2)
-I/O
-I/O
R
(1,2)
15R
7R

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70V261L25PFG Summary of contents

Page 1

Features True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 25/35/55ns (max.) – Industrial: 25ns (max.) Low-power operation – IDT70V261S Active: 300mW (typ.) Standby: 3.3mW (typ.) – IDT70V261L Active: 300mW (typ.) Standby: ...

Page 2

IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Description The IDT70V261 is a high-speed 16K x 16 Dual-Port Static RAM. The IDT70V261 is designed to be used as a stand-alone 256K-bit Dual-Port RAM combination MASTER/SLAVE ...

Page 3

IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Truth Table I: Non-Contention Read/Write Control (1) Inputs R ...

Page 4

IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Absolute Maximum Ratings Symbol Rating (2) V Terminal Voltage TERM with Respect to GND Temperature T BIAS Under Bias Storage T STG Temperature I DC Output OUT Current NOTES: 1. ...

Page 5

IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter Dynamic Operating CC SEM = V Current (Both Ports Active ...

Page 6

IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load Timing of Power-Up Power-Down Electrical Characteristics ...

Page 7

IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Waveform of Read Cycles ADDR CE OE UB, LB R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. ...

Page 8

IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Timing Waveform of Write Cycle No. 1, R/W Controlled Timing ADDRESS OE ( SEM ( SEM ( R/W (4) DATA OUT DATA IN Timing ...

Page 9

IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM I R/W OE NOTES ...

Page 10

IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (M BUSY Access Time from Address Match t BAA BUSY Disable Time ...

Page 11

IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Timing Waveform of Write with R/W "A" BUSY "B" R/W "B" NOTES: must be met for both BUSY input (SLAVE) and output (MASTER BUSY is asserted ...

Page 12

IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS ...

Page 13

IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Truth Table III — Interrupt Flag Left Port 13L 3FFF ...

Page 14

... V per Truth master use the BUSY signal as a write inhibit signal. Thus on the IDT70V261 SRAM the BUSY pin is an output if the part is used as a master (M/S pin = slave (M/S pin = two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array ...

Page 15

... How the Semaphore Flags Work The semaphore logic is a set of eight latches which are indepen- dent of the Dual-Port SRAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “ ...

Page 16

IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides ...

Page 17

IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Ordering Information XXXXX A A 999 Device Power Speed Package Type NOTES: 1. For other speeds, packages and powers contact your sales office. 2. Green parts available. For specific speeds, ...

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