GS880E18AT-133 GSI TECHNOLOGY, GS880E18AT-133 Datasheet

GS880E18AT-133

Manufacturer Part Number

GS880E18AT-133

Description

Manufacturer

GSI TECHNOLOGY

Datasheet

1.GS880E18AT-133.pdf (24 pages)

Specifications of GS880E18AT-133

Density

9Mb

Access Time (max)

8.5ns

Sync/async

Synchronous

Architecture

SDR

Clock Freq (max)

117.6MHz

Operating Supply Voltage (typ)

2.5/3.3V

Address Bus

19b

Package Type

TQFP

Operating Temp Range

0C to 70C

Number Of Ports

Supply Current

125mA

Operating Supply Voltage (min)

2.3/3V

Operating Supply Voltage (max)

2.7/3.6V

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

100

Word Size

18b

Number Of Words

512K

Lead Free Status / Rohs Status

Not Compliant

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline

• Dual Cycle Deselect (DCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

Functional Description

Applications

The GS880E18/32/36AT is a 9,437,184-bit (8,388,608-bit for

x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

Rev: 1.03 11/2004

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

operation

Flow Through

Pipeline

3-1-1-1

2-1-1-1

9Mb Synchronous Burst SRAMs

512K x 18, 256K x 32, 256K x 36

Curr

tCycle

(x32/x36)

(x18)

Parameter Synopsis

1/24

-250

280

330

175

200

2.5

4.0

5.5

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

DCD Pipelined Reads

The GS880E18/32/36AT is a DCD (Dual Cycle Deselect)

pipelined synchronous SRAM. SCD (Single Cycle Deselect)

versions are also available. DCD SRAMs pipeline disable

commands to the same degree as read commands. DCD RAMs

hold the deselect command for one full cycle and then begin

turning off their outputs just after the second rising edge of

clock.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS880E18/32/36AT operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

from the internal circuits and are 3.3 V and 2.5 V compatible.

-225

255

300

165

190

2.7

4.4

6.0

GS880E18/32/36AT-250/225/200/166/150/133

-200

230

270

160

180

3.0

5.0

6.5

DDQ

-166

200

230

150

170

3.4

6.0

7.0

) pins are used to decouple output noise

-150

185

215

145

165

3.8

6.7

7.5

-133

165

190

135

150

4.0

7.5

8.5

Unit

250 MHz–133 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS880E18AT-133

GS880E18AT-133 Summary of contents

Page 1

... DDQ -166 -150 -133 Unit 3.0 3.4 3.8 4.0 ns 5.0 6.0 6.7 7.5 ns 230 200 185 165 mA 270 230 215 190 mA 6.5 7.0 7.5 8.5 ns 6.5 7.0 7.5 8.5 ns 160 150 145 135 mA 180 170 165 150 mA © 2001, GSI Technology DD ...

Page 2

... V 4 DDQ DDQ DDQ DQP DDQ Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 GS880E18A 100-Pin TQFP Pinout (Package T) 512K x 18 Top View 2/ DDQ DQP DDQ DDQ DDQ © 2001, GSI Technology ...

Page 3

... DDQ DDQ DDQ DDQ Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 GS880E32A 100-Pin TQFP Pinout (Package T) 256K x 32 Top View 3/ DDQ DDQ DDQ DDQ © 2001, GSI Technology ...

Page 4

... V 27 DDQ DQP Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 GS880E36A 100-Pin TQFP Pinout (Package T) 256K x 36 Top View 4/24 DQP DDQ DDQ DDQ DDQ DQP 51 A © 2001, GSI Technology ...

Page 5

... Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply 5/24 © 2001, GSI Technology ...

Page 6

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 GS880E18/32/36A Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q DCD=1 6/24 A Memory Array – DQx1 DQx9 © 2001, GSI Technology ...

Page 7

... Interleaved Burst Sequence 10 11 1st address 11 00 2nd address 00 01 3rd address 01 10 4th address Note: The burst counter wraps to initial state on the 5th clock. 7/24 Function Linear Burst Interleaved Burst Active Standby A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 © 2001, GSI Technology ...

Page 8

... C D Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 and/or B may be used in any combination with BW to write single or multiple bytes Notes © 2001, GSI Technology ...

Page 9

... Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 State Diagram Key None X H None X L None Next CR X Next CR H Next CW X Next 9/24 2 ADSP ADSC ADV © 2001, GSI Technology High-Z X High-Z X High ...

Page 10

... ADSP is tied high and ADV is tied low. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Simplified State Diagram X Deselect First Write Burst Write CR CW 10/ First Read Burst Read BW, and GW) control inputs, and © 2001, GSI Technology ...

Page 11

... Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Simplified State Diagram with G X Deselect First Write Burst Write 11/ First Read Burst Read CR © 2001, GSI Technology ...

Page 12

... Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 2001, GSI Technology Unit Notes ...

Page 13

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 13/24 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 2001, GSI Technology ...

Page 14

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Overshoot Measurement and Timing 50% V Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 14/24 50% tKC Typ. Max. Unit 30pF © 2001, GSI Technology ...

Page 15

Page 16

Page 17

... GSI Technology -133 Unit Min Max 7.5 — ns 4.0 ns — 1.5 — ns 1.5 ns — 1.5 — ns 0.5 ns — 8.5 — ns 8.5 ns — ...

Page 18

... Read C+1 Read C+2 Read C+3 Cont tKL tKL tKH tKH tKC tKC ADSC initiated read and E3 only sampled with ADSC tS tKQ tOHZ tH tLZ Q(A) D(B) 18/24 Deselect Deselect Deselected with E1 tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2001, GSI Technology tKQX ...

Page 19

... Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read masks ADSP E1 masks ADSP tH tS tOHZ tLZ Q(A) D(B) Q(C) 19/24 Deselect tH Deselected with E1 tKQX tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2001, GSI Technology ...

Page 20

... Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Sleep Mode Timing Diagram tKH tKH tKC tKC tKL tKL tZZS tZZH 20/24 2. The duration of SB tZZR © 2001, GSI Technology ...

Page 21

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 θ 0.10 0.15 1.40 1.45 0.30 0.40 0.20 — e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 21/ © 2001, GSI Technology ...

Page 22

... GS880E36AT-133 512K x 18 GS880E18AT-250I 512K x 18 GS880E18AT-225I 512K x 18 GS880E18AT-200I 512K x 18 GS880E18AT-166I 512K x 18 GS880E18AT-150I 512K x 18 GS880E18AT-133I 256K x 32 GS880E32AT-250I 256K x 32 GS880E32AT-225I 256K x 32 GS880E32AT-200I 256K x 32 GS880E32AT-166I 256K x 32 GS880E32AT-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880E18AT-150IT. ...

Page 23

... GS880E36AT-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880E18AT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user ...

Page 24

... Updated AC Test Conditions table and removed Output Load 2 diagram • Removed Preliminary banner Content • Removed pin locations from pin description table • Updated format Format/Content • Updated timing diagrams • Updated mechanical drawings 24/24 Page;Revisions;Reason © 2001, GSI Technology ...

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