CY7C0831AV-133BBI Cypress Semiconductor Corp, CY7C0831AV-133BBI Datasheet - Page 5

• Manufacturer Part Number: CY7C0831AV-133BBI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0831AV-133BBI

• Density: 2Mb
• Access Time (max): 4.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 300mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 18b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

Pin Definitions
Byte Select Operation
Document #: 38-06059 Rev. *S
A
ADS
CE0
CE1
CLK
CNTEN
CNTRST
CNT/MSK
DQ
OE
INTL
CNTINT
R/W
B
0L
0L
0L
L
–A
–B
Left Port
L
L
L
L
L
[8]
[7]
–DQ
[8]
18L
1L
L
L
[8]
L
[2]
[9]
17L
[7]
L
[7]
MRST
TMS
TDO
TCK
V
V
TDI
DD
SS
A
ADS
CE0
CE1
CLK
CNTEN
CNTRST
CNT/MSK
DQ
OE
INTR
CNTINT
R/W
B
0R
0R
Right Port
0R
R
–A
–B
R
R
R
R
R
[8]
[7]
–DQ
[8]
18R
1R
R
Control Pin
R
[8]
R
[9]
[2]
R
17R
[7]
[7]
B
B
0
1
Address Inputs.
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for
the part using the externally supplied address on the address pins and for loading this address
into the burst address counter.
Active LOW Chip Enable Input.
Active HIGH Chip Enable Input.
Clock Signal. Maximum clock input rate is f
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are
asserted LOW.
Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the
burst address counter of its respective port. CNTRST is not disabled by asserting ADS or
CNTEN.
Address Counter Mask Register Enable Input. Asserting this signal LOW enables access to
the mask register. When tied HIGH, the mask register is not accessible and the address counter
operations are enabled based on the status of the counter control signals.
Data Bus Input/Output.
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data
pins during Read operations.
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations are used for message passing. INT
right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is
deasserted HIGH when it reads the contents of its mailbox.
Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter
is incremented to all ‘1s.’
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port
memory array.
Byte Select Inputs. Asserting these signals enables Read and Write operations to the corre-
sponding bytes of the memory array.
Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting
MRST LOW performs all of the reset functions as described in the text. A MRST operation is
required at power up.
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers.
JTAG Test Clock Input.
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
Ground Inputs.
Power Inputs.
Description
MAX
CY7C0832BV, CY7C0833AV
.
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
DQ
DQ
9–17
0–8
Effect
Byte Control
Byte Control
L
is asserted LOW when the
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