LT1806CS6 Linear Technology, LT1806CS6 Datasheet - Page 17

• Manufacturer Part Number: LT1806CS6
• Manufacturer: Linear Technology
• Type: General Purpose Amplifierr

Specifications of LT1806CS6

• Rail/rail I/o Type: Rail to Rail Input/Output
• Number Of Elements: 1
• Unity Gain Bandwidth Product: 325MHz
• Slew Rate: 125V/us
• Common Mode Rejection Ratio: 79dB
• Input Offset Voltage: 700uV
• Input Bias Current: 4uA
• Single Supply Voltage (typ): 3/5/9/12V
• Dual Supply Voltage (typ): ±3/±5V
• Voltage Gain In Db: 106.85dB
• Power Supply Rejection Ratio: 90dB
• Power Supply Requirement: Single/Dual
• Shut Down Feature: Yes
• Single Supply Voltage (min): 2.5V
• Single Supply Voltage (max): 12.6V
• Dual Supply Voltage (min): ±1.25V
• Dual Supply Voltage (max): ±6.3V
• Technology: BiCOM
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 6
• Package Type: TSOT-23
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIONS INFORMATION
Rail-to-Rail Characteristics
The LT1806/LT1807 have input and output signal range that
covers from negative power supply to positive power sup-
ply. Figure 1 depicts a simplifi ed schematic of the amplifi er.
The input stage is comprised of two differential amplifi ers,
a PNP stage Q1/Q2 and a NPN stage Q3/Q4 that are active
over different ranges of common mode input voltage. The
PNP differential pair is active between the negative supply
to approximately 1.5V below the positive supply. As the
input voltage moves closer toward the positive supply, the
transistor Q5 will steer the tail current I
mirror Q6/Q7, activating the NPN differential pair. The PNP
pair becomes inactive for the rest of the input common
mode range up to the positive supply.
SHDN
V
V
+
–
V
V
+
–
ESDD5
ESDD6
D9
R6
40k
R7
100k
Q16
GENERATION
BIAS
Q17
ESDD1
ESDD4
+IN
–IN
V
V
+
–
V
V
+
–
Figure 1. LT1806 Simplifi ed Schematic Diagram
ESDD2
ESDD3
1
D6
D5
to the current
D8
D7
Q4
Q7
D1
D2
Q3
Q5
A pair of complementary common emitter stages Q14/Q15
that enable the output to swing from rail to rail constructs
the output stage. The capacitors C1 and C2 form the
local feedback loops that lower the output impedance at
high frequency. These devices are fabricated on Linear
Technology’s proprietary high speed complementary
bipolar process.
Power Dissipation
The LT1806/LT1807 amplifi ers combine high speed with
large output current in a small package, so there is a need
to ensure that the die’s junction temperature does not
exceed 150°C. The LT1806 is housed in an SO-8 package
or a 6-lead SOT-23 package and the LT1807 is in an SO-8
Q6
V
BIAS
Q1
+
D3
D4
Q2
I
1
Q10
Q11
Q9
R3
R1
Q12
LT1806/LT1807
Q8
R4
R2
C
C
+
V
OUTPUT BIAS
Q13
–
R5
BUFFER
I
2
AND
C2
C1
18067 F01
17
Q15
Q14
18067fc
OUT