FW21154AE Intel, FW21154AE Datasheet
FW21154AE
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FW21154AE Summary of contents
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PCI-to-PCI Bridge Specification Update July 2004 Notice: The 21154 may contain design defects or errors known as errata which may cause the behavior of the 21154 to deviate from published specifications. Current characterized errata are documented in this specification ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. ...
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Contents Revision History ......................................................................................... 5 Preface....................................................................................................... 8 Summary Table of Changes..................................................................... 10 Identification Information.......................................................................... 14 Errata ....................................................................................................... 15 Specification Changes ............................................................................. 22 Specification Clarifications ....................................................................... 23 Documentation Changes ......................................................................... 24 Specification Update 21154 PCI-to-PCI Bridge iii ...
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... Tval description,Section 1 Updated Errata #1 title description in Table , “Errata” on page 11 worst-case conditions for Tval description,Section page 11. “Specification Changes” on page 11. Updated status for Erratas 1 “Secondary Clocks Outputs Conditions”. Moved 20. page 23. and added new on page 15 and added on page 15 Intel Confidential5 ...
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... Date Version 5/8/01 4/30/01 12/15/00 11/13/00 10/02/00 6Intel Confidential Added information for AE and BE versions of the 21154 product Updated Errata #5 AC Marking state in Updated status state for Errata #4, #5, #6, and #8 in and in descriptions in “Errata” on page 15 Updated descriptions for Errata #1 and #3 in Added last two rows to Table 1, “ ...
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... Added clamp circuit errata. Tsetup test conditions found to be invalid. Device meets 3 ns Tsetup limit on all pins. Added updated boundary scan order pin list. This is the new Specification Update document. It contains all identified errata published prior to this date. Revision History Intel Confidential7 ...
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... Affected Documents/Related Documents 21154 PCI-to-PCI Bridge Datasheet 21154 PCI-to-PCI Bridge Configuration Application Note 21154 PCI-to-PCI Bridge Hardware Implementation Application Note 21154 PCI-to-PCI Bridge Evaluation Board User’s Guide 8Intel Confidential Title 21154 PCI-to-PCI Bridge Specification Update Order 278108 278080 ...
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... Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (data sheets, manuals, etc.). 21154 PCI-to-PCI Bridge Specification Update Preface Intel Confidential9 ...
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... Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the 21154 PCI-to-PCI Bridge product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notations: ...
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... Problems or Hangs when P_VIO = 3.3V Secondary Address pins are driven incorrectly during reset. SPECIFICATION CHANGES PBGA Package Dimensions for Coplanarity Changed from Maximum Value 0. Maximum Value of 0.2 mm PCI Configuration Space Registers have changed. Pin 1 Designator Change Power Management Capability Change Intel Confidential11 ...
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... Summary Table of Changes Specification Clarifications No 12Intel Confidential Markings Page Status Doc 21154 PCI-to-PCI Bridge Specification Update SPECIFICATION CLARIFICATIONS Signal trst_l must be driven low to disable JTAG for normal operation ...
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... Updated Version of PCI Local Bus Specification 35 Doc Section 4.1, Updated s_clk and p_clk description 35 Doc Section 4.2, Updated Clock Outputs 35 Doc Section 4.4.1, Added Note at End of Section. Section 4.5, Table 5 Product Part Numbers have been 36 Doc updated. 36 Doc Updated Version of PCI Local Bus Specification Intel Confidential13 ...
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... Digital Semiconductor 21154AA DC1062B Digital Semiconductor 21154AB DC1062C Intel 21154AC DC1113A Intel 21154BC DC1113A Intel 21154AC DC1113B Intel 21154BC DC1113B Intel FW21154AE Intel FW21154BE a. Identified in a PCI system by reading the value in the REV_ID register. 14Intel Confidential REV_ID Register Package Type Speed (MHz) ...
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... Any improvement in the thermal factors (Oja), board design, Worst-case Slow Condition 1 6 data 1 <6 junction temperature. 10. Errata V (V) dd 3.0 3 junction o C junction temperature. Tval V_V (ns) Tval Z_V (ns) 8.0 No data <6.25 7.35 Intel Confidential15 o C ...
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... Board Specification” of the PCI Local Bus Specification, Revision 2.2 are not affected. Designs whose topology might include long bus lengths might find that connecting s_vio or p_vio to 5 volts leads to improved signal integrity for the corresponding bus. As such, Intel recommends thorough signal integrity analyses prior to a decision on which voltage to connect to these pins. ...
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... PCI component. i. for a 33Mhz bridge. These values should be chosen based on the rise time of the power supply and the frequency of the on board pulse source. The values given for R1, R3, and C1 are for example purposes only. 21154 PCI-to-PCI Bridge Specification Update Errata Intel Confidential17 ...
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... The Vcc ramp rate and R1,C1 time constant determine the duration and amplitude of the pulses generated during power up. The R2-R3 values are chosen based on applicable board etch impedance-matching requirements. 18Intel Confidential R1 47K R3 ...
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... Tgsval. Note: This errata does not apply when operating at 33 MHz or if the external shift register is not used and msk_in is grounded enabling all secondary clocks. 21154 PCI-to-PCI Bridge Specification Update V CC External Clock S_CLK R3 S_CLK_O Errata A8363-01 Intel Confidential19 ...
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... Problem: Intel has received reports of performance problems due to excessive retries and hangs in a few applications when P_VIO and/or S_VIO =3.3V. The retry issue has been observed in several types Video, Fibre Channel and Gigabit Ethernet modules with the time to failure ranging from 7 minutes to 39 hours ...
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... This contention may cause excessive power dissipation in the 21154 and could potentially damage the device. There is no known work around. Workaround: No Fix Status: 21154 PCI-to-PCI Bridge Specification Update Errata clock cycles), discards Intel Confidential21 ...
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... Description Pin Number Previous Name Previous Function New Name Function Operation Vdd Vss a. 00000 indicates that the device behind the bridge does not support PME#. 22Intel Confidential Offset 00:01 02:03 08 Value D11 Vdd Power Input pmeena_l Input This can be tied to either Vdd or Vss (ground). This effects the value of bits [31:27], PME_SUP, of the Power Management Register (dword address DCh, offset DEh) ...
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... The signal trst_l resets the JTAG circuitry while asserted low. This signal also enables normal JTAG TAP controller operation when high. For normal PCI-to-PCI bridge operation, disable JTAG by pulling trst_l low using a 5K resistor. 21154 PCI-to-PCI Bridge Specification Update Specification Clarifications Intel Confidential23 ...
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... Section 18.0, Figure 25 title is changed to read as follows: 304-Point PBGA Package (2-Layer and 4-Layer) 4. Section 18.0, Table 51, 304-Point 2-Layer PBGA Package Dimensions Section 18.0, Table 51 title is changed to read as follows: 304-Point PBGA Package Dimensions (2-Layer and 4-Layer) 24Intel Confidential is changed from 2.2W to 2.9W. wc Parameter j wc ...
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... V 148/149 ss p_cbe_l<2> 149/150 p_frame_l 150/151 p_irdy_l 151/152 p_trdy_l 152/153 p_devsel_l 153/154 p_stop_l 154/155 p_lock_l 155/156 V 156/157 ss Documentation Changes By Group Disable Group Disable Cell — — — Group Disable — — Group Disable — Group Disable 1 Intel Confidential25 ...
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... Y13 AA14 AB14 AC14 AA15 AB15 Y15 AC15 AA16 AB16 AA17 AB17 Y17 AB18 AC18 AA18 AC19 AA19 26Intel Confidential Signal Name Boundary Scan Order p_perr_l 157/158 p_serr_l 158/159 p_par 159/160 p_cbe_l<1> 160/161 p_ad<15> 161/162 p_ad<14> 162/163 p_ad<13> 163/164 p_ad<12> 164/165 p_ad< ...
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... V 215/216 ss p_ad<33> 216/217 p_ad<32> 217/218 p_par64 218/219 config66 219/220 msk_in 220/221 Documentation Changes By Group Disable Group Disable Cell — Group Disable — — Intel Confidential27 ...
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... The controller will reset synchronously after five TCK clock cycles, with TMS held high.. Figure 5. Signal trst_l States Note: During normal 21154 operation the JTAG logic must be disabled by pulling trst_l low using a 5K ohm resistor. 28Intel Confidential trst_l JTAG Enabled JTAG Reset 21154 PCI-to-PCI Bridge Specification Update ...
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... Ω pull-down resistor is required on trst_l for normal PCI-to-PCI bridge operation. However, some JTAG test results may be inconclusive if the 5 K Ω resistor remains in the circuit. To obtain accurate JTAG results, Intel recommends one of the following solutions: • Verify that the JTAG test equipment, after driving trst_l low to reset the TAP controller, constantly drives trst_l high during JTAG tests. If this signal is not constantly driven high, the 5 K Ω ...
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... Example of GPIO Clock Mask Implementation on the System Board s_clk_<9> 13. Section 10.2, Secondary Clock Control, Figure 20 This figure now appears as follows: Figure 20. Clock Mask and Load Shift Timing gpio[0] gpio[2] msk_in 30Intel Confidential msk_in 21154 gpio<0> gpio<2> Bit 15 21154 PCI-to-PCI Bridge Specification Update ...
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... Bit 13 s_clk_o<9> feedback to the 21154 s_clk_o input. To enable s_clk_o<9> in all cases the D5 input of the shift register is grounded, to Vss. 6. Bit 12 s_clk_o<8> is disabled. 7. Bit 11 s_clk_o<7> is disabled. 8. Bit 10 s_clk_o<6> is disabled. 9. Bit 9 s_clk_o<5> is disabled. 21154 PCI-to-PCI Bridge Specification Update Description and the timing diagram in Figure 21. Documentation Changes s_clk_o Output Not applicable Intel Confidential31 ...
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... Shifted gpio<2> msk_in 16. Section 15.1.3, Primary Command Register, Table Description Changed the description in Dword 0 for when one. It now appears as follows: Primary Command Register Dword Bit 0 I/O space enable 32Intel Confidential Name R/W Controls the 21154’s response to I/O transactions on the primary interface ...
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... Slot 2 PRSNT#<1:0> or device 2 <3:2> Slot 1 PRSNT#<1:0> or device 1 <1:0> Slot 0PRSNT#<1:0> or device 0 18. Section 4.4.1, Serial Clock Mask Shift, Figure 3 Figure 3 has been updated as follows: 21154 PCI-to-PCI Bridge Specification Update Documentation Changes Description s_clk_o Output Not applicable Not applicable Intel Confidential33 ...
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... Clock Mask Load and Shift Timing gpio[0] gpio[2] msk_in 20. Section 4.2, 21154 Output Clocks This note has been added to the end of the section: Note: Intel recommends that a 22K pull-up resistor be placed on s_clk to better insure proper initialization on power-up. 34Intel Confidential msk_in 21154 gpio<0> gpio<2> ...
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... Section 4.4.1, Added Note at End of Section. The note added to the end of Section 4.4.1 appears as follows: Note: Refer to Errata #7 previously in this document for an explanation of an added external buffer on the output of gpio <2> to use this feature at 66 MHz. 21154 PCI-to-PCI Bridge Specification Update Documentation Changes Intel Confidential35 ...
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... National Semiconductor IDC 29. Updated Version of PCI Local Bus Specification All references in the 21154 PCI-to-PCI Bridge documentation where the PCI Local Bus Specification is mentioned were updated from version 2.2 to version 2.3. 36Intel Confidential Part Number (5V) Part Number (3.3V) CDC328A CDCV304 CGS74B2525 CGS574CT2524 ...