GS8160Z36T-133 GSI TECHNOLOGY, GS8160Z36T-133 Datasheet

GS8160Z36T-133

Manufacturer Part Number

GS8160Z36T-133

Description

Manufacturer

GSI TECHNOLOGY

Datasheet

1.GS8160Z36T-133.pdf (24 pages)

Specifications of GS8160Z36T-133

Density

18Mb

Access Time (max)

8.5ns

Sync/async

Synchronous

Architecture

SDR

Clock Freq (max)

117.6MHz

Operating Supply Voltage (typ)

2.5/3.3V

Address Bus

19b

Package Type

TQFP

Operating Temp Range

0C to 70C

Number Of Ports

Supply Current

140mA

Operating Supply Voltage (min)

2.3/3V

Operating Supply Voltage (max)

2.7/3.6V

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

100

Word Size

36b

Number Of Words

512K

Lead Free Status / Rohs Status

Not Compliant

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Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

Functional Description

The GS8160Z18/36T is an 18Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other

pipelined read/double late write or flow through read/single

late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

Rev: 2.17 11/2004

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

Through

Pipeline

3-1-1-1

2-1-1-1

18Mb Pipelined and Flow Through

3.3 V

2.5 V

Flow

3.3 V

2.5 V

Synchronous NBT SRAM

Curr

tCycle

(x32/x36)

(x18)

Parameter Synopsis

1/24

-250 -225 -200 -166 -150 -133 Unit

280

330

275

320

175

200

175

200

2.5

4.0

5.5

255

300

250

295

165

190

165

190

2.7

4.4

6.0

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8160Z18/36T may be configured by the user to operate

in Pipeline or Flow Through mode. Operating as a pipelined

synchronous device, meaning that in addition to the rising edge

triggered registers that capture input signals, the device

incorporates a rising-edge-triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS8160Z18/36T is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

Standard 100-pin TQFP package.

230

270

230

265

160

180

160

180

3.0

5.0

6.5

200

230

195

225

150

170

150

170

GS8160Z18/36T-250/225/200/166/150/133

3.4

6.0

7.0

185

215

180

210

145

165

145

165

3.8

6.7

7.5

165

190

165

185

135

150

135

150

4.0

7.5

8.5

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS8160Z36T-133

GS8160Z36T-133 Summary of contents

Page 1

... Curr 200 190 180 170 (x32/x36) 1/ 3.3 V I/O 3.8 4.0 ns 6.7 7.5 ns 185 165 mA 215 190 mA 180 165 mA 210 185 mA 7.5 8.5 ns 7.5 8.5 ns 145 135 mA 165 150 mA 145 135 mA 165 150 mA © 1998, GSI Technology DD ...

Page 2

... DDQ DDQ DDQ DQP DDQ Rev: 2.17 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 GS8160Z18T Pinout Top View 2/ DDQ DQP DDQ DDQ DDQ © 1998, GSI Technology ...

Page 3

... DQP DDQ DDQ DDQ DDQ DQP Rev: 2.17 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 GS8160Z36T Pinout 512K x 36 Top View 3/24 DQP DDQ DDQ DDQ DDQ DQP 51 A © 1998, GSI Technology ...

Page 4

... Byte D Data Input and Output pins Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low Core power supply Ground Output driver power supply 4/24 ; active low A9 ; active low B9 ; active low C9 ; active low D9 © 1998, GSI Technology ...

Page 5

... GS8160Z18/36 NBT SRAM Functional Block Diagram Rev: 2.17 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Amps Sense Drivers Write 5/24 © 1998, GSI Technology ...

Page 6

... Rev: 2.17 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 & determine which bytes will be written. All or none may be activated. A write and E ). Deassertion of any one of the Enable © 1998, GSI Technology ...

Page 7

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 External L Next L External L Next L External L Next L Next L None L None L None L None L None L None Current L 7/ High High High-Z 1,2,3, High High High High High High © 1998, GSI Technology Notes 1,10 2 1,2,10 3 1,3, ...

Page 8

... and D represent input command codes ,as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipeline and Flow Through Read/Write Control State Diagram 8/24 New Write Burst Write B D n+3 ƒ ƒ © 1998, GSI Technology ...

Page 9

... and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 9/24 Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 1998, GSI Technology ...

Page 10

... Pipeline and Flow Through Read Write Control State Diagram 10/ Data Out W (Q Valid) D Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes as indicated in the Truth Tables. n+2 n+3 ƒ ƒ © 1998, GSI Technology ...

Page 11

... Note: The burst counter wraps to initial state on the 5th clock. 11/24 Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby High Drive (Low Impedance) Low Drive (High Impedance) A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 © 1998, GSI Technology ...

Page 12

... Rev: 2.17 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Sleep Mode Timing Diagram tKH tKH tKL tKL tZZS tZZH DD 12/24 2. The duration of SB tZZR pipelined parts and V on flow DDQ SS © 1998, GSI Technology ...

Page 13

... GS8160Z18/36T-250/225/200/166/150/133 Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 1998, GSI Technology Unit Notes ...

Page 14

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 14/24 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 1998, GSI Technology ...

Page 15

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Overshoot Measurement and Timing 50% V Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 15/24 50% tKC Typ. Max. Unit 30pF © 1998, GSI Technology ...

Page 16

Page 17

Page 18

... GSI Technology -133 Unit Min Max 7.5 ns — — 4.0 ns 1.5 — ns 1.5 — ns 1.5 ns — 0.5 — ns 8.5 ns — — 8 ...

Page 19

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Pipeline Mode Timing (NBT) Suspend Read C Write D writeno-op tKH tKH tKC tKC tKL tKL D(A) Q(B) Q(C) 19/24 Read E Deselect E tLZ tHZ tKQ tKQX D(D) Q(E) © 1998, GSI Technology ...

Page 20

... Flow Through Mode Timing (NBT) Write B+1 Read C Cont tKL tKL tKH tKH tKC tKC C D tKQ tLZ D(B) D(B+1) Q(C) tOHZ 20/24 Read D Write E Read F Write tKQ tKQX tHZ tLZ Q(D) D(E) Q(F) tOLZ tOE © 1998, GSI Technology tKQX D(G) ...

Page 21

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 θ 0.10 0.15 1.40 1.45 0.30 0.40 0.20 — e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 21/ © 1998, GSI Technology ...

Page 22

... GS8160Z36T-166I 512K x 36 GS8160Z36T-150I 512K x 36 GS8160Z36T-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816Z36-166IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 23

... Updated DQ on page 19 • Updated DQ on page 21 • Updated Pin Description table • Updated Operating Currents table Content • Updated table on page 1; updated power numbers • Updated Recommended Operating Conditions table (added V references) DDQ 23/24 in pin description table. SS © 1998, GSI Technology ...

Page 24

... Removed Preliminary banner Content • Removed pin locations from pin description table • Corrected pin Content • Updated format Content/Format • Corrected block diagram • Added parity designator (“P”) to Pin 1 on x36 Content/Format • Updated format Content/Format 24/24 © 1998, GSI Technology ...

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