LP2995LQ National Semiconductor, LP2995LQ Datasheet

LP2995LQ

Manufacturer Part Number
LP2995LQ
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of LP2995LQ

Voltage Regulator Type
Linear
Topology
LDO
Number Of Outputs
Single
Input Voltage (min)
2.2V
Input Voltage (max)
5.5V
Package Type
LLP EP
Output Current
1.5A
Load Regulation
0.5%
Operating Temp Range
0C to 125C
Operating Temperature Classification
Commercial
Pin Count
16
Mounting
Surface Mount
Quiescent Current (max)
400uA
Lead Free Status / Rohs Status
Not Compliant

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© 2011 National Semiconductor Corporation
DDR Termination Regulator
General Description
The LP2995 linear regulator is designed to meet the JEDEC
SSTL-2 and SSTL-3 specifications for termination of DDR-
SDRAM. The device contains a high-speed operational am-
plifier to provide excellent response to load transients. The
output stage prevents shoot through while delivering 1.5A
continuous current and transient peaks up to 3A in the appli-
cation as required for DDR-SDRAM termination. The LP2995
also incorporates a V
lation and a V
DDR DIMMS.
Patents Pending
Typical Application Circuit
REF
output as a reference for the chipset and
SENSE
pin to provide superior load regu-
200393
LP2995
Features
Applications
Low output voltage offset
Works with +5v, +3.3v and 2.5v rails
Source and sink current
Low external component count
No external resistors required
Linear topology
Available in SO-8, PSOP-8 or LLP-16 packages
Low cost and easy to use
DDR Termination Voltage
SSTL-2
SSTL-3
20039302
March 28, 2011
www.national.com

Related parts for LP2995LQ

LP2995LQ Summary of contents

Page 1

... SENSE lation and a V output as a reference for the chipset and REF DDR DIMMS. Patents Pending Typical Application Circuit © 2011 National Semiconductor Corporation LP2995 Features ■ Low output voltage offset ■ Works with +5v, +3.3v and 2.5v rails ■ ...

Page 2

... EP Ordering Information Order Number Package Type LP2995M LP2995MX LP2995MR PSOP-8 LP2995MRX PSOP-8 LP2995LQ LP2995LQX www.national.com 20039320 20039350 Name NC No internal connection. Can be used for vias. GND Ground. VSENSE Feedback pin for regulating VTT. VREF Buffered internal reference voltage of VDDQ/2. VDDQ Input for internal reference equal to VDDQ/2 ...

Page 3

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. AVIN to GND PVIN to GND VDDQ (Note 2) Storage Temp. Range Junction Temperature PSOP-8 Thermal Resistance (θ Electrical Characteristics apply over the full Operating Temperature Range (T AVIN = PVIN = 2 ...

Page 4

Typical Performance Characteristics (25° (0, 25, 85, and 125° Temperature (No Load) REF www.national.com Iq vs Temperature ( V 20039309 20039311 OUT 20039313 4 = 2.5V) ...

Page 5

OUT Maximum Output Current (Sinking (VDDQ = 2.5) Maximum Output Current (Sourcing (VDDQ = 2.5) 20039315 IN 20039317 5 IN 20039316 www.national.com ...

Page 6

Block Diagram Description The LP2995 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2 and SSTL-3. The LP2995 is capable of sinking and sourcing current at the out- put V , regulating the voltage to ...

Page 7

Pin Descriptions AVIN AND PVIN AVIN and PVIN are the input supply pins for the LP2995. AVIN is used to supply all the internal control circuitry for the two op-amps and the output stage PVIN is used ...

Page 8

Thermal Dissipation Since the LP2995 is a linear regulator any current flow from V will result in internal power dissipation generating heat prevent damaging the part from exceeding the maximum allowable junction temperature, care should be taken to ...

Page 9

Typical Application Circuits The typical application circuit used for SSTL-2 termination schemes with DDR-SDRAM can be seen in For SSTL-3 and other applications it may be desirable to change internal reference voltage scaling from VDDQ * 0.5. An external resistor ...

Page 10

PCB Layout Considerations 1. AVIN and PVIN should be tied together for optimal performance. A local bypass capacitor should be placed as close as possible to the PVIN pin. 2. GND should be connected to a ground plane with multiple ...

Page 11

Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Package (M8) NS Package Number M08A 11 www.national.com ...

Page 12

LLP Package (LD) NS Package Number LQA16A 8-Lead PSOP Package (PSOP-8) NS Package Number MRA08A 12 ...

Page 13

Notes 13 www.national.com ...

Page 14

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