M24C08-WDW6T STMicroelectronics, M24C08-WDW6T Datasheet - Page 17

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M24C08-WDW6T

Manufacturer Part Number
M24C08-WDW6T
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of M24C08-WDW6T

Density
8Kb
Interface Type
Serial (I2C)
Organization
1Kx8
Access Time (max)
900ns
Frequency (max)
400KHz
Write Protection
Yes
Data Retention
40Year
Operating Supply Voltage (typ)
3.3/5V
Package Type
TSSOP
Operating Temp Range
-40C to 85C
Supply Current
2mA
Operating Supply Voltage (min)
2.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Lead Free Status / Rohs Status
Not Compliant

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M24C16, M24C08, M24C04, M24C02, M24C01
3.7.2
3.7.3
3.7.4
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a Device Select Code with the Read/Write bit (RW) set to 1. The device
acknowledges this, and outputs the byte addressed by the internal address counter. The
counter is then incremented. The bus master terminates the transfer with a Stop condition,
as shown in
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the 9
time, the device terminates the data transfer and switches to its Stand-by mode.
th
Figure
bit time. If the bus master does not drive Serial Data (SDA) Low during this
9, without acknowledging the byte.
Figure
9.
Device operation
17/33

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