W39V040AP Winbond Electronics, W39V040AP Datasheet
W39V040AP
Specifications of W39V040AP
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W39V040AP Summary of contents
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... Boot Block Lockout Enable Acquisition Flow................................................................ CHARACTERISTICS .......................................................................................................... 18 7.1 Absolute Maximum Ratings .......................................................................................... 18 7.2 Programmer Interface Mode DC Operating Characteristics......................................... 18 7.3 LPC Interface Mode DC Operating Characteristics...................................................... 19 7.4 Power-up Timing........................................................................................................... 19 7.5 Capacitance .................................................................................................................. 19 W39V040A Data Sheet 512K × 8 CMOS FLASH MEMORY WITH LPC INTERFACE Publication Release Date: June 21, 2005 - 1 - Revision A6 ...
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PROGRAMMER INTERFACE MODE AC CHARACTERISTICS ............................................. 20 8.1 AC Test Conditions ....................................................................................................... 20 8.2 AC Test Load and Waveform ....................................................................................... CHARACTERISTICS .......................................................................................................... 21 9.1 Read Cycle Timing Parameters.................................................................................... 21 9.2 Write Cycle Timing Parameters .................................................................................... 21 ...
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... This device can operate at two modes, Programmer bus interface mode and LPC bus interface mode the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But in the LPC interface mode, this device complies with the Intel LPC specification ...
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PIN CONFIGURATIONS A7(GPI1) A6(GPI0) A5(#WP) A4(#TBL) A3(RSV) A2(RSV) A1(RSV) A0(RSV) DQ0(LAD0 MODE 5 A10(GPI4) 6 R/#C(CLK #RESET 10 A9(GPI3 A8(GPI2) A7(GPI1) 13 ...
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BLOCK DIAGRAM #WP #TBL LPC CLK Interface LAD[3:0] #LFRAME IC #INIT #RESET R/#C A[10:0] Program- mer DQ[7:0] Interface #OE #WE 5. PIN DESCRIPTION INTERFACE SYM. PGM MODE * #RESET * #INIT #TBL #WP CLK GPI[4:0] ID[3:0] LAD[3:0] #LFRAM R/#C ...
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... Programmer mode; while the MODE pin is set to low DD position the LPC mode. In Programmer mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed. The row address is mapped to the higher internal address A[18:11] ...
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On the other hand, if the DQ2 is "1", it means the #TBL pin is tied to low state, then boot block is locked no matter how the software is set. Like the DQ2, the DQ3 ...
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Hardware Data Protection The integrity of the data stored in the W39V040A is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than duration will not initiate a write cycle. ...
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GPI Register BIT 7 − Alternative GPI Register Memory Address Table ID[2:0] PINS 000 001 010 011 100 101 110 111 6.12.2 Product Identification Registers There is an alternative software method (six commands bytes) ...
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The ROM responds to top 512K byte pages based on the ID pins strapping according to the following table: ID[2:0] PINS 000 001 010 011 100 101 110 111 6.14 Table of Operating Modes 6.14.1 Operating Mode Selection - Programmer ...
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Standard LPC Memory Cycle Definition NO. OF FIELD CLOCKS Start 1 "0000b" appears on LPC bus to indicate the initial Cycle Type & "010Xb" indicates memory read cycle; while "011xb" indicates memory write 1 Dir cycle. "X" mean don't ...
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SA = 7XXXXh for Unique Sector7 (Boot Sector 6XXXXh for Unique Sector6 SA = 5XXXXh for Unique Sector5 SA = 4XXXXh for Unique Sector4 6. PA: Page Address PA = 7FXXXh for Page 15 in Sector 7 PA ...
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Embedded Programming Algorithm Increment Address Program Command Sequence (Address/Command): Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit No Last Address ? Yes Programming Completed 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data Publication Release Date: June 21, 2005 ...
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Embedded Erase Algorithm Write Erase Command Sequence #Data Polling or Toggle Bit Successfully Completed Chip Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H 5555H/10H Start (see below) Erasure Completed Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H ...
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Embedded #Data Polling Algorithm Read Byte (DQ0 - DQ7) Address = VA No DQ7 = Data 6.19 Embedded Toggle Bit Algorithm Start VA = Byte address for programming = Any of the sector addresses within the sector being erased ...
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Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Load data 55 to address 2AAA Load data 90 to address 5555 μ Pause 10 S Notes for software ...
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Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 ...
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DC CHARACTERISTICS 7.1 Absolute Maximum Ratings PARAMETER Power Supply Voltage Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential Transient Voltage (<20 nS) on Any Pin to Ground Potential Note: Exposure to conditions ...
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LPC Interface Mode DC Operating Characteristics = 3.3V ± 0.3V ° 0V PARAMETER SYM. Power Supply Current I CC CMOS Standby Isb1 Current TTL Standby Current Isb2 ...
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PROGRAMMER INTERFACE MODE AC CHARACTERISTICS 8.1 AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 8.2 AC Test Load and Waveform D OUT 30 pF (Including Jig and Scope) 1 TTL Gate and ...
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AC CHARACTERISTICS 9.1 Read Cycle Timing Parameters = 3.3V ± 0.3V ° 0V PARAMETER Read Cycle Time Row/Column Address Set Up Time Row/Column Address Hold Time Address ...
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TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE 10.1 Read Cycle Timing Diagram #RESET T RST A[10:0] R/# #WE #OE High-Z DQ[7:0] 10.2 Write Cycle Timing Diagram T RST #RESET Column Address A[10: R/#C #OE #WE DQ[7:0] ...
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Timing Waveforms for Programmer Interface Mode, continued 10.3 Program Cycle Timing Diagram A[10:0] 5555 (Internal A[18:0]) DQ[7:0] R/#C # #WE Byte 0 Note: The internal address A[18:0] are converted from external Column/Row address Column/Row Address are mapped to ...
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Timing Waveforms for Programmer Interface Mode, continued 10.5 Toggle Bit Timing Diagram A[10:0] R/#C #WE #OE DQ6 10.6 Boot Block Lockout Enable Timing Diagram A[10:0] 5555 (Internal A[18:0]) DQ[7:0] AA R/#C # #WE T WPH SB0 Note: The ...
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Timing Waveforms for Programmer Interface Mode, continued 10.7 Chip Erase Diagram Six-byte code for 3.3V-only software chip erase A[10:0] 5555 (Internal A[18:0]) AA DQ[7:0] R/#C # #WE T SB0 Note: The internal address A[18:0] are converted from external ...
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LPC INTERFACE MODE AC CHARACTERISTICS 11.1 AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Slew Rate Input/Output Timing Level Output Load 11.2 Read/Write Cycle Timing Parameters = 3.3V ± 0.3V ° ...
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TIMING WAVEFORMS FOR LPC INTERFACE MODE 12.1 Read Cycle Timing Diagram CLK #RESET #LFRAM Memory Read Start Cycle 0000b A[31:28] A[27:24] 010Xb LAD[3:0] 1 Clock 1 Clock 12.2 Write Cycle Timing Diagram CLK #RESET #LFRAM Memory Write Start Cycle ...
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Timing Waveforms for LPC Interface Mode, continued 12.3 Program Cycle Timing Diagram CLK #RESET #LFRAM Memory Write 1st Start Cycle LAD[3:0] 0000b XXXXb 011Xb 1 Clock 1 Clock CLK #RESET #LFRAM Memory Write 2nd Start Cycle 0000b XXXXb 011Xb LAD[3:0] ...
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Timing Waveforms for LPC Interface Mode, continued 12.4 #DATA Polling Timing Diagram CLK #RESET #LFRAM Memory Write Cycle 1st Start LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CLK #RESET #LFRAM Memory Read Start Cycle 0000b XXXXb 010Xb XXXXb ...
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Timing Waveforms for LPC Interface Mode, continued 12.5 Toggle Bit Timing Diagram CLK #RESET #LFRAM Memory Write Cycle 1st Start 0000b LAD[3:0] 011Xb XXXXb 1 Clock 1 Clock CLK #RESET #LFRAM Memory Read Start Cycle 0000b 010Xb XXXXb LAD[3:0] 1 ...
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Timing Waveforms for LPC Interface Mode, continued 12.6 Boot Block Lockout Enable Timing Diagram CLK #RESET #LFRAM Memory Write Cycle 1st Start LAD[3:0 0000b XXXXb 011Xb ] 1 Clock 1 Clock CLK #RESET #LFRAM Memory Write Cycle 2nd Start 0000b ...
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Timing Waveforms for LPC Interface Mode, continued 12.7 Chip Erase Timing Diagram CLK #RESET #LFRAM Memory Write Cycle 1st Start LAD[3:0] 0000b XXXXb 011Xb 1 Clock 1 Clock CLK #RESET #LFRAM Memory Write Cycle 2nd Start LAD[3:0] 0000b 011Xb XXXXb ...
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Timing Waveforms for LPC Interface Mode, continued 12.8 Sector Erase Timing Diagram CLK #RESET #LFRAM Memory Write Cycle 1st Start 0000b LAD[3:0] 011Xb XXXXb 1 Clock 1 Clock CLK #RESET #LFRAM Memory Write 2nd Start Cycle 0000b 011Xb XXXXb LAD[3:0] ...
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Timing Waveforms for LPC Interface Mode, continued 12.9 Page Erase Timing Diagram CLK #RESET #LFRAM Memory Write Cycle 1st Start 0000b XXXXb LAD[3:0] 011Xb 1 Clock 1 Clock CLK #RESET #LFRAM Memory Write Cycle 2nd Start 0000b 011Xb XXXXb LAD[3:0] ...
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Timing Waveforms for LPC Interface Mode, continued 12.10 GPI Register Readout Timing Diagram CLK #RESET #LFRAM Memory Read Start Cycle 0000b 010Xb 1111b LAD[3:0] 1111b Load Address "FFBXE100(hex)" Clock 1 Clock Note: Read the DQ[4:0] to ...
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... TIME PART NO. (NS) W39V040AP W39V040AQ W39V040AT W39V040APZ W39V040AQZ W39V040ATZ Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. ...
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... Seating Plane G E 15.2 32L STSOP mm θ Symbol Notes: 1. Dimensions D & not include interlead flash Dimension b1 does not include dambar protrusion/intrusio 3. Controlling dimension: Inches 4. General appearance spec. should be based on final Symbol Publication Release Date: June 21, 2005 - 37 - W39V040A Dimension in Inches Dimension in mm Min ...
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Package Dimensions, continued 15.3 40L TSOP ( mm) 16. REVISION HISTORY VERSION DATE A1 Oct. 8, 2002 A2 Dec. 16, 2002 A3 Nov. 19, 2003 A4 Sep. 14, 2004 1, 2, 34, 36 Add Lead free part ...
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Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other ...