CY7C68300A-56LFXC Cypress Semiconductor Corp, CY7C68300A-56LFXC Datasheet - Page 17

• Manufacturer Part Number: CY7C68300A-56LFXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68300A-56LFXC

• Lead Free Status / Rohs Status: Compliant

Table 6-6. EEPROM Organization (continued)
7.0
The following recommendations should be followed to ensure
reliable high-performance operation.
Source for recommendations:
Document #: 38-08031 Rev. *E
0xEA to
0xFF
EEPROM
• At least a four-layer impedance controlled boards are
• Specify impedance targets (ask your board vendor what
• To control impedance, maintain trace widths and trace
• Minimize stubs to minimize reflected signals.
• Connections between the USB connector shell and signal
• Bypass/flyback caps on VBus, near connector, are
• DPLUS and DMINUS trace lengths should be kept to within
• Maintain a solid ground plane under the DPLUS and
• It is preferred is to have no vias placed on the DPLUS or
• Isolate the DPLUS and DMINUS traces from all other signal
• EZ-USB FX2 PCB Design Recommendations,
• High-speed USB Platform Design Guidelines,
Address
required to maintain signal quality.
they can achieve).
spacing.
ground must be done near the USB connector.
recommended.
2 mm of each other in length, with preferred length of 20-
30mm.
DMINUS traces. Do not allow the plane to be split under
these traces.
DMINUS trace routing.
traces by no less than 10 mm.
http:///www.cypress.com/cfuploads/support/app_notes/FX
2_PCB.pdf.
http://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf
PCB Layout Recommendations
Unused ROM Space
Via hole for thermally connecting the
QFN to the circuit board ground plane.
Field Name
Figure 8-1. Cross-Section of the Area Underneath the QFN Package
Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI
PCB Material
This part is not recommended for new designs
Amount of unused ROM space will vary depending on strings.
Cu Fill
.
Bridge for new designs
Solder Mask
0.013” dia
0.017” dia
Field Description
8.0
Package Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the
heat transfer area below the package to provide a good
thermal bond to the circuit board. A Copper (Cu) fill is to be
designed into the PCB as a thermal pad under the package.
Heat is transferred from the CY7C68300A through the
device’s metal paddle on the bottom side of the package. Heat
from here is conducted to the PCB at the thermal pad. It is then
conducted from the thermal pad to the PCB inner ground plane
by a 5 x 5 array of Via. A Via is a plated through-hole in the
PCB with a finished diameter of 13 mil. The QFN’s metal die
paddle must be soldered to the PCB’s thermal pad. Solder
mask is placed on the board top side over each Via to resist
solder flow into the Via. The mask on the top side also
minimizes outgassing during the solder reflow process.
For further information on this package design please refer to
the application note “Surface Mount Assembly of AMKOR’s
MicroLeadFrame (MLF) Technology.” This application note
can be downloaded from AMKOR’s website from the following
URL
http://www.amkor.com/products/notes_papers/MLF_AppNote
_0301.pdf. The application note provides detailed information
on board mounting guidelines, soldering flow, rework process,
etc.
Figure 8-1 below displays a cross-sectional area underneath
the package. The cross section is of only one via. The solder
paste template needs to be designed to allow at least 50%
solder coverage. The thickness of the solder paste template
should be 5 mil. It is recommended that “No Clean,” type 3
solder paste is used for mounting the part. Nitrogen purge is
recommended during reflow.
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and
the Ground Plane
Cu Fill
Quad Flat Package No Leads (QFN)
PCB Material
Required
Contents
CY7C68300A
Page 17 of 21
Suggested
Contents
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