WJCE6353 Intel, WJCE6353 Datasheet - Page 17

• Manufacturer Part Number: WJCE6353
• Description: COFDM Terrestrial Demodulator 64-Pin LQFP
• Manufacturer: Intel

Specifications of WJCE6353

• Pin Count: 64
• Screening Level: Commercial
• Package Type: LQFP
• Package: 64LQFP
• Operating Temperature: -10 to 80 °C
• Lead Free Status / Rohs Status: Compliant

3.2
3.2.1
Figure 7 - DVB Transport Packet Header Byte
After decoding the 188-byte MPEG packet, it is output on the MDO pins in 188 consecutive clock cycles.
Additionally when the TEI_En bit in the OP_CTRL_0 register (0x5A) is set high (default), the TEI bit of any uncorrectable
packet will automatically be set to ‘1’. If TEI_En bit is low then TEI bit will not be changed (but note that if this bit is already
1, for example, due to a channel error which has not been corrected, it will remain high at output).
*. Or 27.00 MHz clock
†. Cb = the total capacitance on either clock or data line in pF to maximum of 400pF.
CLK clock frequency (Primary)
Bus free time between a STOP and START
condition.
Hold time (repeated) START condition.
LOW period of CLK clock.
HIGH period of CLK clock.
Set-up time for a repeated START condition.
Data hold time (when input).
Data set-up time
Rise time of both CLK and DATA signals.
Fall time of both CLK and DATA signals, (100pF to
ground).
Set-up time for a STOP condition.
MPEG
Data Output Header Format
Parameter
MDO[7]
Transport
TEI
0
Packet
Header
4 bytes
1
Table 4 - Timing of 2-Wire Bus
0
184 Transport packet bytes
f
t
t
t
t
t
t
t
t
t
t
Symbol
CLK
BUFF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
R
F
SU;STO
188 byte packet output
0
Intel Corporation
CE6353
0
Values with 4MHz clock
250
1
Min.
0
4.7
4.0
4.7
4.0
4.7
0
4.0
1
MDO[0]
1000
100
300
1
Max.
3.45
1st byte
2nd byte
20 + 0.1C
20 + 0.1C
100
Values with 20.48 MHz
0
1.3
0.6
1.3
0.6
0.6
0
0.6
Min.
clock
b
b
†
†
*
400
300
300
Max.
0.9
Data Sheet
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
Unit
17