SI2107-D-FM Silicon Laboratories Inc, SI2107-D-FM Datasheet - Page 31

• Manufacturer Part Number: SI2107-D-FM
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2107-D-FM

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

When gain adjustments are made, the device allows up
to 100 µs for the gain changes to settle before
beginning the next measurement.
To facilitate a rapid initial acquisition, Si2107/08/09/10
includes an acquisition mode wherein the measurement
window size is reduced by a factor of 64 when
compared to the normal tracking mode.
During the AGC search, the device is in acquisition
mode, and the gain is adjusted until the measured
signal power crosses the desired threshold or a limit is
reached. If the signal power crosses the threshold
before reaching a limit, the search completes, and the
AGCL bit is asserted. If a gain limit is reached, the
device asserts both the AGCL bit and the AGCF bit.
In the normal tracking mode, the device continuously
measures the input signal power according to the AGC
measurement window size. If the absolute value of the
difference between the AGCTH and AGCPWR exceeds
the value of the AGC tracking threshold, AGCTR, the
AGC loop adjusts gain settings until the AGCPWR level
matches AGCTH.
The AGC gain offset register, AGCO, provides the
ability to apply a static gain offset to the input channel.
Silicon Laboratories will provide the recommended
values for this register. It is possible to read out the
instantaneous settings of each of the four VGAs from
the AGC<n>, <n = 1..4>, registers. These values may
be used to estimate the input power to the device as
described in AN298.
6.6.2. Digital AGC
Downstream of the analog VGAs, after A/D conversion
of the signal, there are two points at which the digital
gain can be programmed. Digital AGC1 is used to
change signal power after removal of adjacent channels
LNA
MIXER
VGA1
Figure 16. Analog AGC Control Loop
VGA2
LPF
Rev. 1.0
by the (digital) anti-aliasing filter.
By default, DAGC1 is enabled and periodically adjusts
the gain of the I & Q data streams based on a
comparison of the measured complex RMS level and a
target value. The target value can be selected with the
DAGC1T register. Two levels are provided to allow
operation with additional headroom for signal peaks
during signal acquisition. The gain function of DAGC1
can be disabled using DAGC1_EN; then, no gain is
applied to I & Q data streams. The signal measurement
and gain adjustment normally operate continuously,
allowing the gain to track the input level. The
measurement window can be adjusted by register
DAGC1W. The automatic updating of the gain can be
frozen by register bit DAGC1HOLD. This holds the gain
to the last setting. The value of the gain can be read
from the DAGC1 register. It is possible to override the
internal AGC algorithm and provide host-based control
of AGC1 by appropriately programming register bit
DAGC1HOST.
Digital AGC2 (DAGC2) is intended to optimally scale the
soft decision outputs of the demodulator prior to Viterbi
decoding. This allows it to compensate for signal level
variations after matched filtering and equalization.
Normally, operation is continuous, but tracking can be
disabled using register bit DAGC2_TDIS. This holds the
gain to the last setting.
During AGC operation, the average power of the signal
is compared to a threshold set by register DAGC2T. The
signal power is measured over a finite window specified
by DAGC2W. The gain applied to the signal to make the
input match the programmed threshold can be read
from register DAGC2GA.
OFFSET
AGC
A/D
Si2107/08/09/10
AGC Threshold
rms calculator
31