RFB433B Micrel Inc, RFB433B Datasheet - Page 4

• Manufacturer Part Number: RFB433B
• Manufacturer: Micrel Inc

Specifications of RFB433B

• Operating Frequency (max): 434000kHz
• Operating Temperature (min): -20C
• Operating Temperature Classification: Commercial
• Modulation Type: FSK
• Operating Supply Voltage (typ): 3V
• Lead Free Status / Rohs Status: Not Compliant

Programming
A two-line bus is used to program the circuit; the two
lines being CLK and REG. The 2-line serial bus interface
allows control over the frequency dividers and the
selective powering up of Tx, Rx and Synthesizer circuit
blocks. After power on the PUEXT should be held low
while loading in the control word for the first time. When
the control word has been loaded, the PUEXT is brought
Table 1: Bit allocation
Table 2: Bit description
Name
A1
A0
N1
N0
M1
M0
Pa2
Pa1
Pa0
Gc
ByLNA
Ref6
Ref5
Ref4
Ref3
Ref2
Ref1
Ref0
Cpmp1
Cpmp0
RT
Pu
p1 – p6
Ref2
Pa1
p59
p67
p75
A1
‘0’
Strandveien 13, N-1366 Lysaker, Norway. Tel: [phone] Fax: [phone] E-mail:
p7 – p12
Description
frequency divider A1, 6 bits
frequency divider A0, 6 bits
frequency divider N1, 12 bits
frequency divider N0, 12 bits
frequency divider M1, 10 bits
frequency divider M0, 10 bits
gain setting in power amplifier
pa2, pa1, pa0 = 0 : lowest output power
pa2, pa1, pa0 = 1 : highest output power
gain control in power amplifier buffer,1=high gain
1 = the Low Noise Amplifier (LNA) is bypassed
reference settings in lock detector
all 0’s: highest reference
all 1’s: lowest reference
charge pump
setting:
0 = receive mode 1 = transmit mode
1 = power up, 0 = power down (When Pu=1, power down is controlled by PuExt)
Ref1
Pa0
p60
p68
p76
A0
‘0’
p13 – p24
Ref0
p61
p69
p77
N1
Gc
‘0’
Cpmp1=0, Cpmp0=0 : 125uA
Cpmp1=0, Cpmp0=1 : 500uA
Cpmp1=1, Cpmp0=0 : controlled by LD (LD) LD=0: 500uA, LD=1: 125uA
Cpmp1=1, Cpmp0=1 : same as previous in Tx. In Rx the current is 500 A.
p25 – p36
ByLNA
Cpmp1
p62
p70
p78
N0
‘0’
p37 – p46
high for t h e rest of the power on cycle. The interface
consists of an 80-bit programming register. Data is
entered on the RegIn line with the most significant bit
first. The first bit entered is called p1, the last one p80.
The bits in the programming register are arranged as
shown
Cpmp0
Ref6
p63
p71
p79
M1
RT
[e-mail]
p47 – p56
Ref5
p64
p72
p80
M0
Pu
‘1’
Orgnr. NO 929 510 909 www.bluechip.no
in
Ref4
p57
p65
p73
’0’
‘0’
Ref3
Pa2
p58
p66
p74
‘0’
table1.