ATA5811-PLQX Atmel, ATA5811-PLQX Datasheet - Page 50

• Manufacturer Part Number: ATA5811-PLQX
• Manufacturer: Atmel

Specifications of ATA5811-PLQX

• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Height (mm): 0.9mm
• Product Length (mm): 7mm
• Lead Free Status / Rohs Status: Compliant

Figure 40. Flow Chart Polling Mode/RX Mode (T_MODE = 1, Transparent Mode Inactive)
50
ATA5811/ATA5812 [Preliminary]
Start-up mode:
NO
Receiving mode:
The incomming data stream is passed via the TX/RX Data Buffer to the
connected microcontroller. If an bit error occurs the transceiver is set back to
Start-up mode.
Output level on pin RX_ACTIVE -> High
I
S
Sleep mode:
All circuits for analog signal processing are disabled. Only XTO and Polling logic
is enabled.
Output level on pin RX_ACTIVE -> Low; I
T
Bit-check mode:
The incomming data stream is analyzed. If the timing indicates a valid transmitter
signal, the control bits VSOUT_EN, CLK_ON and OPM0 are set to 1 and the
transceiver is set to receiving mode. Otherwise it is set to Sleep mode or to
Start-up mode.
Output level on Pin RX_ACTIVE -> High
I
T
S
= I
Sleep
Bit-check
Start-up signal processing:
The signal processing circuit are enabled.
Output level on pin RX_ACTIVE -> High; I
T
= I
Start-up PLL:
The PLL is enabled and locked.
Output level on pin RX_ACTIVE -> High; I
Start RX Mode
Startup_Sig_Proc
RX_X
RX_X
= Sleep
OPM0 = 1
T
SLEEP
1024
?
?
YES
YES
= 0
T
Start RX Polling Mode
DCLK
written into the TX/RX
RX data stream is
X
NO
YES
Sleep
Data Buffer
detected ?
Bit error ?
Start bit
NO
NO
S
YES
= I
S
S
IDLE_X
= I
= I
Set VSOUT_EN = 1
RX_X
Set CLK_ON = 1
Startup_PLL_X
Set OPM0 = 1
P_MODE = 0
Bit check
Set IRQ
OK ?
NO
NO
?
YES
YES
;T
Startup_PLL
Sleep:
X
T
T
T
T
DCLK
Startup_PLL
Startup_Sig_Proc
Bit-check
Sleep
:
:
:
:
:
Defined by bits Sleep0 to Sleep4 in Control
Register 4
Defined by bit XSleep in Control Register 4
Basic clock cycle
798.5
882
498
306
210
Is defined by the selected baud rate range and
T
Baud0 and Baud1 in Control Register 6.
Depends on the result of the bit check.
If the bit check is ok, T
number of bits to be checked (N
on the utilized data rate.
If the bit check fails, the average time period for
that check depends on the selected baud-rate
range and on T
defined by bit Baud0 and Baud1 in Control
Register 6.
If the transceiver detects a bit error after a
successful bit check and before the start bit is
detected pin IRQ will be set to high (only if
P_MODE=0) and the transceiver is set back to
start-up mode.
DCLK
. The baud-rate range is defined by bit
T
T
T
T
DCLK
DCLK
DCLK
T
DCLK
DCLK
(typ)
XDCLK
. The baud-rate range is
(BR_Range 0)
(BR_Range 1)
(BR_Range 2)
(BR_Range 3)
Bit-check
depends on the
Bit-check
) and
4689B–RKE–04/04