CLC5903VLA/HALF National Semiconductor, CLC5903VLA/HALF Datasheet - Page 23

• Manufacturer Part Number: CLC5903VLA/HALF
• Manufacturer: National Semiconductor

Specifications of CLC5903VLA/HALF

• Lead Free Status / Rohs Status: Compliant

Condensed CLC5903 Address Map
DEC_BY_4
SCALE
GAIN_A
GAIN_B
RATE
SERIAL_CTRL
FREQ_A
PHASE_A
FREQ_B
PHASE_B
SOURCE
AGC_CTRL
AGC_COUNT
AGC_IC_A
AGC_IC_B
AGC_RB_A
AGC_RB_A
TEST_REG
DEBUG
AGC_TABLE
F1_COEFF
F2_COEFF
F1_CTRL
F2_CTRL
SERIAL_CTRL2
AGC_CTRL2
Register Name
Addr
128
159
160
181
182
245
246
247
248
249
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
31
1
2
3
4
5
6
7
8
9
Addr
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1F
0x80
0x9F
0xA0
0xB5
0xB6
0xF5
0xF6
0xF7
0xF8
0xF9
Hex
FMT1
AgcIcA7
AgcIcB7
AgcRbA7
AgcRbB7
Test7
Rate7
FA7
FA15
FA23
FA31
PA7
PA15
FB7
FB15
FB23
FB31
PB7
PB15
Reserved
Reserved
DITH_B
Bit7
Rate6
FMT0
FA6
FA14
FA22
FA30
PA6
PA14
FB6
FB14
FB22
FB30
PB6
PB14
Reserved
Reserved
AgcIcA6
AgcIcB6
AgcRbA6
AgcRbB6
Test6
DITH_A
The AGC Table loads from the low address to the high address in this order:
“1st location, 2nd location…”
The FIR Coefficients load from the low address to the high address in this order:
“1st location low byte, 1st location high byte, 2nd location…”
The Page Select bits determine which set of coefficient memory is written.
ExtDelay4
Bit6
23
(Continued)
Sc5
Rate5
Packed
FA5
FA13
FA21
FA29
PA5
PA13
FB5
FB13
FB21
FB29
PB5
PB13
AgcLG1
Reserved
Reserved
AgcIcA5
AgcIcB5
AgcRbA5
AgcRbB5
Test5
Test13
TapSel4
ExtDelay3
Bit5
DecBy4
Sc4
Rate4
MuxMode
FA4
FA12
FA20
FA28
PA4
PA12
FB4
FB12
FB20
FB28
PB4
PB12
AgcLG0
Reserved
Reserved
AgcIcA4
AgcIcB4
AgcRbA4
AgcRbB4
Test4
Test12
TapSel3
ExtDelay2
Bit4
Sc3
Rate3
RDY_POL
FA3
FA11
FA19
FA27
PA3
PA11
FB3
FB11
FB19
FB27
PB3
PB11
BS1
AgcHldIC
Reserved
Reserved
AgcIcA3
AgcIcB3
AgcRbA3
AgcRbB3
Test3
Test11
TapSel2
ExtDelay1
Bit3
Dec10
Sc2
GA2
GB2
Rate2
SFS_POL
FA2
FA10
FA18
FA26
PA2
PA10
FB2
FB10
FB18
FB26
PB2
PB10
BS0
Reserved
Reserved
Reserved
AgcIcA2
AgcIcB2
AgcRbA2
AgcRbB2
Test2
Test10
TapSel1
PgSelF1
PgSelF2
ExtDelay0
Bit2
Dec9
Sc1
GA1
GB1
Rate1
SCK_POL
FA1
FA9
FA17
FA25
PA1
PA9
FB1
FB9
FB17
FB25
PB1
PB9
AS1
Reserved
Reserved
Reserved
AgcIcA1
AgcIcB1
AgcRbA1
AgcRbB1
Test1
Test9
TapSel0
CfSelF1B
CfSelF2B
SdcEn
CombOrd1
Bit1
www.national.com
Dec8
Sc0
GA0
GB0
Rate0
SOUT_EN
FA0
FA8
FA16
FA24
PA0
PA8
FB0
FB8
FB16
FB24
PB0
PB8
AS0
ExpInh
Reserved
Reserved
AgcIcA0
AgcIcB0
AgcRbA0
AgcRbB0
Test0
Test8
DebugEnable
CfSelF1A
CfSelF2A
SfsMode
CombOrd0
Bit0