MC33179D ON Semiconductor, MC33179D Datasheet - Page 12

Op Amps 2-18V Quad Low Power

MC33179D

Manufacturer Part Number
MC33179D
Description
Op Amps 2-18V Quad Low Power
Manufacturer
ON Semiconductor
Datasheet

Specifications of MC33179D

Number Of Channels
4
Voltage Gain Db
106.02 dB
Common Mode Rejection Ratio (min)
80 dB
Input Voltage Range (max)
Positive Rail - 2 V
Input Voltage Range (min)
Negative Rail + 2 V
Input Offset Voltage
3 mV
Operating Supply Voltage
36 V
Supply Current
1.7 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOIC-14
Maximum Dual Supply Voltage
+/- 18 V
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
No

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compensation capacitor equal to or greater than the input
capacitance of the op amp (10 pF) placed across the
feedback resistor (see Figure 35) can be used to neutralize
that pole and prevent outer loop oscillation. Since the closed
loop transient response will be a function of that
capacitance, it is important to choose the optimum value for
that capacitor. This can be determined by the following
Equation:
where: Z
If a high source of resistance is used (R1 > 1.0 kW), a
R1
O
C C + (1 ) [R1 R2]) 2
is the output impedance of the op amp.
Figure 35. Compensation for
High Source Impedance
+
R2
C
C
C L (Z O R 2 )
R1
Figure 37. Compensation Circuit for
Z
L
High Capacitive Loads
http://onsemi.com
+
(1)
C
C
12
< 1500 pF) the addition of a compensation resistor on the
order of 20 W between the output and the feedback loop will
help to decrease miller loop oscillation (see Figure 36). For
high capacitive loads (C
compensation scheme should be used (see Figure 37). Both
the compensation resistor and the compensation capacitor
affect the transient response and can be calculated for
optimum performance. The value of C
using Equation 1. The Equation to calculate R
For moderately high capacitive loads (500 pF < C
R2
R1
R
C
Figure 36. Compensation Circuit for
Moderate Capacitive Loads
C
R C + Z O
L
+
L
> 1500 pF), a combined
R1 R2
R2
C
can be calculated
R
C
C
is as follows:
C
L
(2)
L

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