M50FW040K1 STMicroelectronics, M50FW040K1 Datasheet - Page 6

• Manufacturer Part Number: M50FW040K1
• Description: Flash 3.6V 4M (512Kx8)
• Manufacturer: STMicroelectronics

Specifications of M50FW040K1

• Data Bus Width: 8 bit
• Memory Type: NOR
• Memory Size: 4 Mbit
• Architecture: Sectored
• Interface Type: Firmware Hub
• Access Time: 11 ns, 50 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 20 mA
• Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-32
• Organization: 512 KB x 8
• Lead Free Status / Rohs Status: No

M50FW040
SUMMARY DESCRIPTION
The M50FW040 is a 4 Mbit (512Kb x8) non-vola-
tile memory that can be read, erased and repro-
grammed. These operations can be performed
using a single low voltage (3.0 to 3.6V) supply. For
fast erasing in production lines an optional 12V
power supply can be used to reduce the erasing
time.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental Pro-
gram or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
Figure 2. Logic Diagram (FWH Interface)
6/41
ID0-ID3
FGPI0-
FGPI4
FWH4
CLK
INIT
RP
IC
4
5
M50FW040
V CC
V SS
V PP
4
FWH0-
FWH3
WP
TBL
AI03623
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Two different bus interfaces are supported by the
memory. The primary interface, the Firmware Hub
(or FWH) Interface, uses Intel’s proprietary FWH
protocol. This has been designed to remove the
need for the ISA bus in current PC Chipsets; the
M50FW040 acts as the PC BIOS on the Low Pin
Count bus for these PC Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in TSOP32 (8 x 14mm),
TSOP40 (10 x 20mm) and PLCC32 packages and
it is supplied with all the bits erased (set to ’1’).
Table 1. Signal Names (FWH Interface)
FWH0-FWH3
FWH4
ID0-ID3
FGPI0-FGPI4
IC
RP
INIT
CLK
TBL
WP
RFU
V
V
V
NC
CC
PP
SS
Input/Output Communications
Input Communication Frame
Identification Inputs
General Purpose Inputs
Interface Configuration
Interface Reset
CPU Reset
Clock
Top Block Lock
Write Protect
Reserved for Future Use. Leave
disconnected
Supply Voltage
Optional Supply Voltage for Fast
Erase Operations
Ground
Not Connected Internally