DS1005-125 Maxim Integrated Products, DS1005-125 Datasheet
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DS1005-125
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DS1005-125 Summary of contents
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... Extended temperature range available DESCRIPTION The DS1005 5-Tap Silicon Delay Line provides five equally spaced taps with delays ranging from 250 ns, with an accuracy 3%, whichever is greater. This device is offered in a standard 14- pin DIP, making it compatible with existing delay line products. Space-saving 8-pin DIPs and 16-pin SOICs are also available ...
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... LOGIC DIAGRAM Figure 1 PART NUMBER DELAY TABLE (t PART NO. TAP 1 DS1005- DS1005- DS1005-100 20 ns DS1005-125 25 ns DS1005-150 30 ns DS1005-175 35 ns DS1005-200 40 ns DS1005-250 50 ns Custom delays available , t ) Table 1 PHL PLH TAP 2 TAP 105 120 ns 100 ns 150 DS1005 TAP 4 TAP 100 ns 100 ns 125 ns ...
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... MIN t 40% of Tap PLH t PLH t PHL t PU Period MIN (0°C to 70° 5.0V ± 5%) CC TYP MAX UNITS 5. 0 25° ± 5 TYP MAX UNITS ns Table 1 ns Table 1 ns 100 TYP MAX UNITS DS1005 NOTES NOTES 25°C) NOTES ...
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... Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input PHL pulse and the 1.5V point on the trailing edge of any tap output pulse DS1005 ...
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... TEST SETUP DESCRIPTION Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1005. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (20 ps resolution) connected between the input and each tap. Each tap is selected and connected to the counter by a VHF switch control unit ...
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... TIMING DIAGRAM: SILICON DELAY LINE Figure 2 DALLAS SEMICONDUCTOR TEST CIRCUIT Figure DS1005 ...