GAL16V8D-7LP Lattice, GAL16V8D-7LP Datasheet - Page 19

• Manufacturer Part Number: GAL16V8D-7LP
• Description: SPLD - Simple Programmable Logic Devices 5V 16 I/O
• Manufacturer: Lattice

Specifications of GAL16V8D-7LP

• Logic Family: GAL
• Number Of Macrocells: 8
• Maximum Operating Frequency: 125 MHz
• Number Of Programmable I/os: 8
• Delay Time: 7.5 ns
• Operating Supply Voltage: 5 V
• Supply Current: 115 mA
• Maximum Operating Temperature: + 75 C
• Minimum Operating Temperature: 0 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• Number Of Product Terms Per Macro: 8
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / Rohs Status: No

Circuitry within the GAL16V8 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (
the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Be-
cause of the asynchronous nature of system power-up, some
Typ. Vref = 3.2V
Power-Up Reset
Input/Output Equivalent Schematics
INPUT/OUTPUT EQUIVALENT SCHEMATICS
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
Typical Input
FEEDBACK/EXTERNAL
INTERNAL REGISTER
Active Pull-up
Circuit
OUTPUT REGISTER
Vref
Q - OUTPUT
t
pr, 1μs MAX). As a result,
CLK
Vcc
Vcc
Vcc (min.)
Vcc
17
t
pr
conditions must be met to provide a valid power-up reset of the
device. First, the V
input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of
As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.
Typ. Vref = 3.2V
Data
Output
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
t
Tri-State
Control
su
Specifications GAL16V8
Feedback
CC
rise must be monotonic. Second, the clock
Typical Output
Vcc
Active Pull-up
Circuit
Feedback
(To Input Buffer)
Vref
t
PIN
PIN
pr time.