74ABT821D NXP Semiconductors, 74ABT821D Datasheet - Page 7
![Flip Flops 10-BIT D-TYPE 3-S](/photos/15/65/156559/soic24_sml.jpg)
74ABT821D
Manufacturer Part Number
74ABT821D
Description
Flip Flops 10-BIT D-TYPE 3-S
Manufacturer
NXP Semiconductors
Datasheet
1.74ABT821D.pdf
(16 pages)
Specifications of 74ABT821D
Number Of Circuits
1
Logic Family
ABT
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
4.6 ns
High Level Output Current
- 32 mA
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOT-137
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
4.5 V
Lead Free Status / Rohs Status
Details
Other names
74ABT821D,602
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74ABT821D
Manufacturer:
PHI
Quantity:
20 000
Company:
Part Number:
74ABT821DB
Manufacturer:
PHILIPS
Quantity:
342
NXP Semiconductors
10. Dynamic characteristics
Table 7.
GND = 0 V; for test circuit, see
11. Waveforms
74ABT821_4
Product data sheet
Symbol Parameter
t
t
t
t
t
t
t
t
t
t
t
t
f
PLH
PHL
PZH
PZL
PHZ
PLZ
su(H)
su(L)
h(H)
h(L)
WH
WL
max
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
OFF-state to HIGH
propagation delay
OFF-state to LOW
propagation delay
HIGH to OFF-state
propagation delay
LOW to OFF-state
propagation delay
set-up time HIGH
set-up time LOW
hold time HIGH
hold time LOW
pulse width HIGH
pulse width LOW
maximum
frequency
Dynamic characteristics
Fig 5.
Figure
Conditions
CP to Qn; see
CP to Qn; see
OEn to Qn; see
OEn to Qn; see
OEn to Qn; see
OEn to Qn; see
Dn to CP; see
Dn to CP; see
Dn to CP; see
Dn to CP; see
CP; see
CP; see
see
V
V
Propagation delay clock input (CP) to output (Qn), clock pulse (CP) width and
maximum clock (CP) frequency
Figure 5
M
OL
8.
= 1.5 V
and V
Figure 5
Figure 5
All information provided in this document is subject to legal disclaimers.
Qn output
CP input
OH
Figure 7
Figure 7
Figure 7
Figure 7
Figure 5
Figure 5
are typical voltage output levels that occur with the output load.
Figure 6
Figure 6
Figure 6
Figure 6
Rev. 04 — 26 March 2010
GND
V
V
OH
OL
V
I
10-bit D-type flip-flop; positive-edge trigger; 3-state
V
M
t
PHL
t
WH
1 / f
V
M
max
25 °C; V
Min
125
2.1
2.8
1.0
2.2
2.7
2.3
2.1
2.1
1.3
1.3
2.9
3.8
t
WL
−0.3
Typ
185
4.1
4.6
3.0
4.1
4.7
4.6
0.5
0.3
1.8
2.8
CC
0
= 5.0 V −40 °C to +70 °C;
Max
t
5.6
6.2
4.5
5.6
6.2
6.1
PLH
-
-
-
-
-
-
-
V
CC
001aac445
Min
74ABT821
125
2.1
2.8
1.0
2.2
2.7
2.3
2.1
2.1
1.3
1.3
2.9
3.8
= 5.0 V ± 0.5 V
© NXP B.V. 2010. All rights reserved.
Max
6.2
6.7
5.3
6.3
6.7
6.5
-
-
-
-
-
-
-
7 of 16
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz