SST39SF040-70-4C-WH Microchip Technology, SST39SF040-70-4C-WH Datasheet - Page 3

• Manufacturer Part Number: SST39SF040-70-4C-WH
• Description: Flash 512K X 8 70ns
• Manufacturer: Microchip Technology

Specifications of SST39SF040-70-4C-WH

• Data Bus Width: 8 bit
• Memory Type: NOR
• Memory Size: 4 Mbit
• Architecture: Sectored
• Interface Type: Parallel
• Access Time: 70 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 25 mA
• Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: TSOP-32
• Organization: 512 KB x 8
• Lead Free Status / Rohs Status: No RoHS Version Available

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data# Polling (DQ
When the SST39SF010A/020A/040 are in the internal Pro-
gram operation, any attempt to read DQ
complement of the true data. Once the Program operation
is completed, DQ
though DQ
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase opera-
tion, any attempt to read DQ
internal Erase operation is completed, DQ
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector- or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 8 for Data# Polling
timing diagram and Figure 17 for a flowchart.
Toggle Bit (DQ
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
and 1s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector- or Chip-
Erase, the Toggle Bit is valid after the rising edge of sixth
WE# (or CE#) pulse. See Figure 9 for Toggle Bit timing dia-
gram and Figure 17 for a flowchart.
Data Protection
The SST39SF010A/020A/040 provide both hardware and
software features to protect nonvolatile data from inadvert-
ent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
V
inhibited when V
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
©2010 Silicon Storage Technology, Inc.
DD
Power Up/Down Detection: The Write operation is
7
may have valid data immediately following the
DD
7
will produce true data. Note that even
is less than 2.5V.
6
)
7
)
7
6
will produce a ‘0’. Once the
will produce alternating 0s
7
will produce the
7
will produce a
3
Software Data Protection (SDP)
The
approved Software Data Protection scheme for all data
alteration operations, i.e., Program and Erase. Any Pro-
gram operation requires the inclusion of a series of three-
byte sequence. The three-byte load sequence is used to
initiate the Program operation, providing optimal protection
from inadvertent Write operations, e.g., during the system
power-up or power-down. Any Erase operation requires the
inclusion of six-byte load sequence. The SST39SF010A/
020A/040 devices are shipped with the Software Data Pro-
tection permanently enabled. See Table 4 for the specific
software command codes. During SDP command
sequence, invalid commands will abort the device to read
mode, within T
Product Identification
The Product Identification mode identifies the device as the
SST39SF040, SST39SF010A, or SST39SF020A and
manufacturer as SST. This mode may be accessed by soft-
ware operations. Users may wish to use the software Prod-
uct Identification operation to identify the part (i.e., using the
device ID) when using multiple manufacturers in the same
socket. For details, Table 4 for software operation, Figure
12 for the software ID entry and read timing diagram and
Figure 18 for the ID entry command sequence flowchart.
TABLE 1: Product Identification
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Exit ID command sequence, which
returns the device to the Read operation. Please note that
the software reset command is ignored during an internal
Program or Erase operation. See Table 4 for software com-
mand codes, Figure 13 for timing waveform and Figure 18
for a flowchart.
Manufacturer’s ID
Device ID
SST39SF010A
SST39SF020A
SST39SF040
SST39SF010A/020A/040
RC.
provide
Address
0000H
0001H
0001H
0001H
S71147-09-000
the
Data Sheet
Data
BFH
B5H
B6H
B7H
JEDEC
T1.2 1147
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