74LVC373APW NXP Semiconductors, 74LVC373APW Datasheet - Page 11
![Latches 3.3V OCTAL D TRANS LATCH 3-S](/photos/15/65/156576/soic20_sml.jpg)
74LVC373APW
Manufacturer Part Number
74LVC373APW
Description
Latches 3.3V OCTAL D TRANS LATCH 3-S
Manufacturer
NXP Semiconductors
Datasheet
1.74LVC373AD112.pdf
(20 pages)
Specifications of 74LVC373APW
Number Of Circuits
8
Logic Type
TTL
Logic Family
LVC
Polarity
Non-Inverting
High Level Output Current
- 24 mA
Propagation Delay Time
3 ns at 3.3 V
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.2 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
Lead Free Status / Rohs Status
Details
Other names
74LVC373APW,112
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVC373APW
Manufacturer:
NXP
Quantity:
20 000
Company:
Part Number:
74LVC373APW,118
Manufacturer:
NXP Semiconductors
Quantity:
1 850
Philips Semiconductors
2003 May 19
handbook, full pagewidth
handbook, full pagewidth
Octal D-type transparent latch with
5 V tolerant inputs/outputs; 3-state
V
V
V
V
V
V
V
V
V
V
M
M
OL
M
M
X
X
Y
Y
OL
= V
= V
= V
= V
= 1.5 V at V
= 0.5V
= 0.5V
= 1.5 V at V
and V
and V
OL
OL
OH
OH
Fig.9 Latch Enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays.
+ 0.1V
+ 0.3 V at V
CC
OH
CC
OH
0.1V
0.3 V at V
are the typical output voltage drop that occur with the output load.
are the typical output voltage drop that occur with the output load.
at V
at V
CC
CC
CC
CC
CC
CC
at V
at V
< 2.7 V.
2.7 V;
2.7 V;
CC
CC
2.7 V;
CC
CC
2.7 V;
2.7 V.
2.7 V;
2.7 V;
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
OFF-to-LOW
Qn output
Qn output
Qn output
LE input
OE input
GND
V OH
V OL
GND
GND
V OH
V I
V CC
V OL
Fig.10 3-state enable and disable times.
V I
enabled
V M
V M
output
t PLZ
t PHL
t PHZ
t W
V X
V M
11
V Y
disabled
output
t PLH
t PZL
t PZH
V M
V M
MNA885
output
enabled
MNA886
Product specification
74LVC373A