74F258ASJ Fairchild Semiconductor, 74F258ASJ Datasheet - Page 2

• Manufacturer Part Number: 74F258ASJ
• Description: Encoders, Decoders, Multiplexers & Demultiplexers Qd 2-Inp Multiplexer
• Manufacturer: Fairchild Semiconductor

Specifications of 74F258ASJ

• Product: Multiplexer
• Logic Family: 74F
• Number Of Bits: 4
• Number Of Lines (input / Output): 2.0 / 3.0
• Propagation Delay Time: 5.3 ns at 5 V
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOP-16
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Input Lines: 2.0
• Number Of Output Lines: 3.0
• Lead Free Status / Rohs Status: No

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Unit Loading/Fan Out
Truth Table
H
L
X
Z
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
LOW Voltage Level
High Impedance
HIGH Voltage Level
Immaterial
Output
Enable
Pin Names
OE
H
L
L
L
L
S
OE
I
I
Z
0a
1a
a
–Z
–I
–I
0d
1d
d
Select
Input
H
H
S
X
L
L
Common Data Select Input
3-STATE Output Enable Input (Active LOW)
Data Inputs from Source 0
Data Inputs from Source 1
3-STATE Inverting Data Outputs
I
X
X
X
H
L
0
Inputs
Data
I
H
X
L
X
X
1
Description
Output
Z
Z
H
H
L
L
2
Functional Description
The 74F258A is a quad 2-input multiplexer with 3-STATE
outputs. It selects four bits of data from two sources under
control of a common Select input (S). When the Select
input is LOW, the I
is HIGH, the I
selected inputs appears at the outputs in inverted form.
The 74F258A is the logic implementation of a 4-pole, 2-
position switch where the position of the switch is deter-
mined by the logic levels supplied to the Select input. The
logic equation for the outputs is shown below:
When the Output Enable input (OE) is HIGH, the outputs
are forced to a high impedance OFF state. If the outputs of
the 3-STATE devices are tied together, all but one device
must be in the high impedance state to avoid high currents
that would exceed the maximum ratings. Designers should
ensure that Output Enable signals to 3-STATE devices
whose outputs are tied together are designed so there is
no overlap.
150/40 (33.3)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1x
U.L.
Z
n
inputs are selected. The data on the
0x
OE • (I
inputs are selected and when Select
1n
• S
3 mA/24 mA (20 mA)
Output I
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
Input I
I
0n
• S)
IH
OH
/I
/I
IL
OL